Search

Samantha N. Wood

Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )

Most Active Art Unit
2915
Art Unit(s)
2914, 2915
Total Applications
1312
Issued Applications
1235
Pending Applications
29
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5688481 [patent_doc_number] => 20060286796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Method of forming a contact in a flash memory device' [patent_app_type] => utility [patent_app_number] => 11/157143 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4365 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286796.pdf [firstpage_image] =>[orig_patent_app_number] => 11157143 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157143
Method of forming a contact in a flash memory device Jun 19, 2005 Issued
Array ( [id] => 334187 [patent_doc_number] => 07507598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Image sensor fabrication method and structure' [patent_app_type] => utility [patent_app_number] => 11/156794 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5889 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/507/07507598.pdf [firstpage_image] =>[orig_patent_app_number] => 11156794 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/156794
Image sensor fabrication method and structure Jun 19, 2005 Issued
Array ( [id] => 288986 [patent_doc_number] => 07547599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Multi-state memory cell' [patent_app_type] => utility [patent_app_number] => 11/138575 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5162 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/547/07547599.pdf [firstpage_image] =>[orig_patent_app_number] => 11138575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/138575
Multi-state memory cell May 25, 2005 Issued
Array ( [id] => 7490230 [patent_doc_number] => 08030099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Method for determining time to failure of submicron metal interconnects' [patent_app_type] => utility [patent_app_number] => 11/596264 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 6727 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030099.pdf [firstpage_image] =>[orig_patent_app_number] => 11596264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/596264
Method for determining time to failure of submicron metal interconnects May 10, 2005 Issued
Array ( [id] => 404616 [patent_doc_number] => 07288445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Double gated transistor and method of fabrication' [patent_app_type] => utility [patent_app_number] => 11/125063 [patent_app_country] => US [patent_app_date] => 2005-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6492 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288445.pdf [firstpage_image] =>[orig_patent_app_number] => 11125063 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/125063
Double gated transistor and method of fabrication May 8, 2005 Issued
Array ( [id] => 534066 [patent_doc_number] => 07176076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials' [patent_app_type] => utility [patent_app_number] => 11/118843 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 13000 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176076.pdf [firstpage_image] =>[orig_patent_app_number] => 11118843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/118843
Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials Apr 28, 2005 Issued
Array ( [id] => 887827 [patent_doc_number] => 07348210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Post bump passivation for soft error protection' [patent_app_type] => utility [patent_app_number] => 10/908084 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3383 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/348/07348210.pdf [firstpage_image] =>[orig_patent_app_number] => 10908084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908084
Post bump passivation for soft error protection Apr 26, 2005 Issued
Array ( [id] => 606802 [patent_doc_number] => 07154169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Substrate for IC package' [patent_app_type] => utility [patent_app_number] => 11/109823 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1268 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/154/07154169.pdf [firstpage_image] =>[orig_patent_app_number] => 11109823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/109823
Substrate for IC package Apr 19, 2005 Issued
Array ( [id] => 6909952 [patent_doc_number] => 20050173710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Method for manufacturing light emitting diode utilizing transparent substrate and metal bonding technology and structure thereof' [patent_app_type] => utility [patent_app_number] => 11/103834 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1872 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20050173710.pdf [firstpage_image] =>[orig_patent_app_number] => 11103834 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/103834
Method for manufacturing light emitting diode utilizing transparent substrate and metal bonding technology and structure thereof Apr 10, 2005 Abandoned
Array ( [id] => 548521 [patent_doc_number] => 07170156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Laminar multi-layer piezoelectric roll component' [patent_app_type] => utility [patent_app_number] => 11/099349 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 2051 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170156.pdf [firstpage_image] =>[orig_patent_app_number] => 11099349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/099349
Laminar multi-layer piezoelectric roll component Apr 3, 2005 Issued
Array ( [id] => 5750963 [patent_doc_number] => 20060220112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'SEMICONDUCTOR DEVICE FORMING METHOD AND STRUCTURE \nFOR RETARDING DOPANT-ENHANCED DIFFUSION' [patent_app_type] => utility [patent_app_number] => 10/907464 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220112.pdf [firstpage_image] =>[orig_patent_app_number] => 10907464 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907464
SEMICONDUCTOR DEVICE FORMING METHOD AND STRUCTURE nFOR RETARDING DOPANT-ENHANCED DIFFUSION Mar 31, 2005 Abandoned
Array ( [id] => 719927 [patent_doc_number] => 07049209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'De-fluorination of wafer surface and related structure' [patent_app_type] => utility [patent_app_number] => 10/907463 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2597 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049209.pdf [firstpage_image] =>[orig_patent_app_number] => 10907463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907463
De-fluorination of wafer surface and related structure Mar 31, 2005 Issued
Array ( [id] => 5751046 [patent_doc_number] => 20060220195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Structure and method to control underfill' [patent_app_type] => utility [patent_app_number] => 11/095693 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2424 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220195.pdf [firstpage_image] =>[orig_patent_app_number] => 11095693 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095693
Structure and method to control underfill Mar 30, 2005 Abandoned
Array ( [id] => 4845971 [patent_doc_number] => 20080182379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Semiconductor Wafer With Low-K Dielectric Layer and Process For Fabrication Thereof' [patent_app_type] => utility [patent_app_number] => 11/910054 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4935 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20080182379.pdf [firstpage_image] =>[orig_patent_app_number] => 11910054 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/910054
Semiconductor wafer with low-K dielectric layer and process for fabrication thereof Mar 30, 2005 Issued
Array ( [id] => 349182 [patent_doc_number] => 07495300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Gas-sensing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/092654 [patent_app_country] => US [patent_app_date] => 2005-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5658 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495300.pdf [firstpage_image] =>[orig_patent_app_number] => 11092654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/092654
Gas-sensing semiconductor devices Mar 29, 2005 Issued
Array ( [id] => 7599485 [patent_doc_number] => 07582963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Vertically integrated system-in-a-package' [patent_app_type] => utility [patent_app_number] => 11/092363 [patent_app_country] => US [patent_app_date] => 2005-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2053 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/582/07582963.pdf [firstpage_image] =>[orig_patent_app_number] => 11092363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/092363
Vertically integrated system-in-a-package Mar 28, 2005 Issued
Array ( [id] => 5700183 [patent_doc_number] => 20060216868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Package structure and fabrication thereof' [patent_app_type] => utility [patent_app_number] => 11/088773 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2334 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20060216868.pdf [firstpage_image] =>[orig_patent_app_number] => 11088773 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088773
Package structure and fabrication thereof Mar 24, 2005 Abandoned
Array ( [id] => 292751 [patent_doc_number] => 07545045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Dummy via for reducing proximity effect and method of using the same' [patent_app_type] => utility [patent_app_number] => 11/087863 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2515 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/545/07545045.pdf [firstpage_image] =>[orig_patent_app_number] => 11087863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/087863
Dummy via for reducing proximity effect and method of using the same Mar 23, 2005 Issued
Array ( [id] => 5700170 [patent_doc_number] => 20060216855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Schottky diode device with aluminium pickup of backside cathode' [patent_app_type] => utility [patent_app_number] => 11/087913 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4683 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20060216855.pdf [firstpage_image] =>[orig_patent_app_number] => 11087913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/087913
Schottky diode device with aluminum pickup of backside cathode Mar 21, 2005 Issued
Array ( [id] => 843524 [patent_doc_number] => 07387951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Method of dicing semiconductor wafer into chips, and apparatus using this method' [patent_app_type] => utility [patent_app_number] => 11/084133 [patent_app_country] => US [patent_app_date] => 2005-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 3667 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/387/07387951.pdf [firstpage_image] =>[orig_patent_app_number] => 11084133 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/084133
Method of dicing semiconductor wafer into chips, and apparatus using this method Mar 20, 2005 Issued
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