
Samantha N. Wood
Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )
| Most Active Art Unit | 2915 |
| Art Unit(s) | 2914, 2915 |
| Total Applications | 1312 |
| Issued Applications | 1235 |
| Pending Applications | 29 |
| Abandoned Applications | 58 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5628844
[patent_doc_number] => 20060145312
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Dual flat non-leaded semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 11/029653
[patent_app_country] => US
[patent_app_date] => 2005-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1858
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20060145312.pdf
[firstpage_image] =>[orig_patent_app_number] => 11029653
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/029653 | Dual flat non-leaded semiconductor package | Jan 4, 2005 | Abandoned |
Array
(
[id] => 668453
[patent_doc_number] => 07094694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-22
[patent_title] => 'Semiconductor device having MOS varactor and methods for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/023623
[patent_app_country] => US
[patent_app_date] => 2004-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 2696
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/094/07094694.pdf
[firstpage_image] =>[orig_patent_app_number] => 11023623
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/023623 | Semiconductor device having MOS varactor and methods for fabricating the same | Dec 28, 2004 | Issued |
Array
(
[id] => 373313
[patent_doc_number] => 07473616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-06
[patent_title] => 'Method and system for wafer bonding of structured substrates for electro-mechanical devices'
[patent_app_type] => utility
[patent_app_number] => 11/022383
[patent_app_country] => US
[patent_app_date] => 2004-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/07/473/07473616.pdf
[firstpage_image] =>[orig_patent_app_number] => 11022383
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/022383 | Method and system for wafer bonding of structured substrates for electro-mechanical devices | Dec 22, 2004 | Issued |
Array
(
[id] => 5908930
[patent_doc_number] => 20060125001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/012553
[patent_app_country] => US
[patent_app_date] => 2004-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 8653
[patent_no_of_claims] => 53
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[pdf_file] => publications/A1/0125/20060125001.pdf
[firstpage_image] =>[orig_patent_app_number] => 11012553
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/012553 | Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same | Dec 14, 2004 | Issued |
Array
(
[id] => 6917897
[patent_doc_number] => 20050095458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Organic electroluminescent device using mixture of phosphorescent material as light-emitting substance'
[patent_app_type] => utility
[patent_app_number] => 11/011434
[patent_app_country] => US
[patent_app_date] => 2004-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 3706
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[pdf_file] => publications/A1/0095/20050095458.pdf
[firstpage_image] =>[orig_patent_app_number] => 11011434
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/011434 | Organic electroluminescent device using mixture of phosphorescent material as light-emitting substance | Dec 14, 2004 | Issued |
Array
(
[id] => 5913020
[patent_doc_number] => 20060128082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Gate control and endcap improvement'
[patent_app_type] => utility
[patent_app_number] => 11/012414
[patent_app_country] => US
[patent_app_date] => 2004-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 3503
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[pdf_file] => publications/A1/0128/20060128082.pdf
[firstpage_image] =>[orig_patent_app_number] => 11012414
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/012414 | Controlling gate formation by removing dummy gate structures | Dec 14, 2004 | Issued |
Array
(
[id] => 6996872
[patent_doc_number] => 20050136650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Method of manufacturing semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/010424
[patent_app_country] => US
[patent_app_date] => 2004-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 5387
[patent_no_of_claims] => 13
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[pdf_file] => publications/A1/0136/20050136650.pdf
[firstpage_image] =>[orig_patent_app_number] => 11010424
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/010424 | Method of manufacturing semiconductor integrated circuit | Dec 13, 2004 | Abandoned |
Array
(
[id] => 7002447
[patent_doc_number] => 20050167760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Semiconductor device having high-voltage and low-voltage operation regions and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/010343
[patent_app_country] => US
[patent_app_date] => 2004-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 5322
[patent_no_of_claims] => 15
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[pdf_file] => publications/A1/0167/20050167760.pdf
[firstpage_image] =>[orig_patent_app_number] => 11010343
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/010343 | Semiconductor device having high-voltage and low-voltage operation regions and method of fabricating the same | Dec 13, 2004 | Abandoned |
Array
(
[id] => 404661
[patent_doc_number] => 07288490
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-10-30
[patent_title] => 'Increased alignment in carbon nanotube growth'
[patent_app_type] => utility
[patent_app_number] => 11/009854
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 5275
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[pdf_file] => patents/07/288/07288490.pdf
[firstpage_image] =>[orig_patent_app_number] => 11009854
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/009854 | Increased alignment in carbon nanotube growth | Dec 6, 2004 | Issued |
Array
(
[id] => 651309
[patent_doc_number] => 07112887
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-26
[patent_title] => 'Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme'
[patent_app_type] => utility
[patent_app_number] => 10/996163
[patent_app_country] => US
[patent_app_date] => 2004-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 2158
[patent_no_of_claims] => 4
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[pdf_file] => patents/07/112/07112887.pdf
[firstpage_image] =>[orig_patent_app_number] => 10996163
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/996163 | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme | Nov 22, 2004 | Issued |
Array
(
[id] => 708712
[patent_doc_number] => 07061079
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Chip package structure and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/904574
[patent_app_country] => US
[patent_app_date] => 2004-11-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/061/07061079.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904574
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904574 | Chip package structure and manufacturing method thereof | Nov 16, 2004 | Issued |
Array
(
[id] => 7162197
[patent_doc_number] => 20050199991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'MULTI-CHIP PACKAGE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 10/904404
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[firstpage_image] =>[orig_patent_app_number] => 10904404
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904404 | Multi-chip package structure | Nov 8, 2004 | Issued |
Array
(
[id] => 5805182
[patent_doc_number] => 20060091535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Fine pitch bonding pad layout and method of manufacturing same'
[patent_app_type] => utility
[patent_app_number] => 10/904283
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904283 | Fine pitch bonding pad layout and method of manufacturing same | Nov 1, 2004 | Abandoned |
Array
(
[id] => 6988736
[patent_doc_number] => 20050087839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same'
[patent_app_type] => utility
[patent_app_number] => 10/975090
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Array
(
[id] => 6931351
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[patent_issue_date] => 2005-12-22
[patent_title] => 'Semiconductor device and fabrication process thereof'
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[firstpage_image] =>[orig_patent_app_number] => 10973440
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973440 | Semiconductor device and fabrication process thereof | Oct 26, 2004 | Issued |
Array
(
[id] => 6915491
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[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Structurally-stabilized capacitors and method of making of same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973343 | Structurally-stabilized capacitors and method of making of same | Oct 26, 2004 | Issued |
Array
(
[id] => 7080576
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[patent_title] => 'Structure and fabrication method of electrostatic discharge protection circuit'
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Array
(
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[patent_title] => 'METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BiCMOS TECHNOLOGY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711486 | Method to build self-aligned NPN in advanced BiCMOS technology | Sep 20, 2004 | Issued |
Array
(
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[patent_title] => 'IC package, inspection method of IC package mounting body, repairing method of IC package mounting body, and inspection pin for IC package mounting body'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/940963 | IC package, inspection method of IC package mounting body, repairing method of IC package mounting body, and inspection pin for IC package mounting body | Sep 14, 2004 | Issued |
Array
(
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[patent_title] => 'Bump structure'
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[firstpage_image] =>[orig_patent_app_number] => 10938594
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/938594 | Bump structure | Sep 12, 2004 | Issued |