Sameh Tawfik

Array ( [id] => 7541608 [patent_doc_number] => 08059456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Programming a NAND flash memory with reduced program disturb' [patent_app_type] => utility [patent_app_number] => 11/806111 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6296 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/059/08059456.pdf [firstpage_image] =>[orig_patent_app_number] => 11806111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4958945 [patent_doc_number] => 20080273369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, and Computing System' [patent_app_type] => utility [patent_app_number] => 11/743557 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9258 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20080273369.pdf [firstpage_image] =>[orig_patent_app_number] => 11743557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4958951 [patent_doc_number] => 20080273375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'INTEGRATED CIRCUIT HAVING A MAGNETIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/743449 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8375 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20080273375.pdf [firstpage_image] =>[orig_patent_app_number] => 11743449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 114171 [patent_doc_number] => 07719882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Advanced MRAM design' [patent_app_type] => utility [patent_app_number] => 11/743453 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7156 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719882.pdf [firstpage_image] =>[orig_patent_app_number] => 11743453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5164417 [patent_doc_number] => 20070286001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Semiconductor integrated circuit with memory redundancy circuit' [patent_app_type] => utility [patent_app_number] => 11/783123 [patent_app_country] => US [patent_app_date] => 2007-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7775 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20070286001.pdf [firstpage_image] =>[orig_patent_app_number] => 11783123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4732561 [patent_doc_number] => 20080049540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Semiconductor memory device comprising data path controller and related method' [patent_app_type] => utility [patent_app_number] => 11/730653 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049540.pdf [firstpage_image] =>[orig_patent_app_number] => 11730653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5246294 [patent_doc_number] => 20070242528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/730675 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8050 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242528.pdf [firstpage_image] =>[orig_patent_app_number] => 11730675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4744527 [patent_doc_number] => 20080089129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Flash memory device with flexible address mapping scheme' [patent_app_type] => utility [patent_app_number] => 11/730511 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3633 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20080089129.pdf [firstpage_image] =>[orig_patent_app_number] => 11730511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4937611 [patent_doc_number] => 20080074928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Nonvolatile memory system and associated programming methods' [patent_app_type] => utility [patent_app_number] => 11/730265 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6453 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074928.pdf [firstpage_image] =>[orig_patent_app_number] => 11730265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4732528 [patent_doc_number] => 20080049507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Flash memory device employing disturbance monitoring scheme' [patent_app_type] => utility [patent_app_number] => 11/730291 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4142 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049507.pdf [firstpage_image] =>[orig_patent_app_number] => 11730291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 174791 [patent_doc_number] => 07660173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Semiconductor memory device and operating method with hidden write control' [patent_app_type] => utility [patent_app_number] => 11/730223 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5526 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/660/07660173.pdf [firstpage_image] =>[orig_patent_app_number] => 11730223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4826137 [patent_doc_number] => 20080229154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Self-referencing redundancy scheme for a content addressable memory' [patent_app_type] => utility [patent_app_number] => 11/717237 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2406 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229154.pdf [firstpage_image] =>[orig_patent_app_number] => 11717237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4818331 [patent_doc_number] => 20080225590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'APPARATUS AND METHOD FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES' [patent_app_type] => utility [patent_app_number] => 11/684655 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4411 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20080225590.pdf [firstpage_image] =>[orig_patent_app_number] => 11684655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4763822 [patent_doc_number] => 20080175033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'METHOD AND SYSTEM FOR IMPROVING DOMAIN STABILITY IN A FERROELECTRIC MEDIA' [patent_app_type] => utility [patent_app_number] => 11/625187 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175033.pdf [firstpage_image] =>[orig_patent_app_number] => 11625187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5257914 [patent_doc_number] => 20070211546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Apparatus and method for controlling test mode of semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/643917 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2979 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20070211546.pdf [firstpage_image] =>[orig_patent_app_number] => 11643917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4987248 [patent_doc_number] => 20070153586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Method for estimating threshold voltage of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/644649 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2176 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153586.pdf [firstpage_image] =>[orig_patent_app_number] => 11644649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4459046 [patent_doc_number] => 07894293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Memory bank arrangement for stacked memory' [patent_app_type] => utility [patent_app_number] => 11/560898 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6811 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/894/07894293.pdf [firstpage_image] =>[orig_patent_app_number] => 11560898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4777325 [patent_doc_number] => 20080285323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Method and Arrangement for Associative Memory Device Based on Ferrofluid' [patent_app_type] => utility [patent_app_number] => 12/091829 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2956 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20080285323.pdf [firstpage_image] =>[orig_patent_app_number] => 12091829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5544354 [patent_doc_number] => 20090154231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Magnetic Random Access Memory and Operating Method of the Same' [patent_app_type] => utility [patent_app_number] => 12/083001 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 18559 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20090154231.pdf [firstpage_image] =>[orig_patent_app_number] => 12083001 [rel_patent_id] =>[rel_patent_doc_number] =>)