Search

Samir Wadie Rizk

Examiner (ID: 680, Phone: (571)272-8191 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112, 2133
Total Applications
1772
Issued Applications
1604
Pending Applications
23
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16844873 [patent_doc_number] => 11016962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Blockchain data storage based on shared nodes and error correction code [patent_app_type] => utility [patent_app_number] => 16/945302 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945302
Blockchain data storage based on shared nodes and error correction code Jul 30, 2020 Issued
Array ( [id] => 16844873 [patent_doc_number] => 11016962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Blockchain data storage based on shared nodes and error correction code [patent_app_type] => utility [patent_app_number] => 16/945302 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945302
Blockchain data storage based on shared nodes and error correction code Jul 30, 2020 Issued
Array ( [id] => 16844873 [patent_doc_number] => 11016962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Blockchain data storage based on shared nodes and error correction code [patent_app_type] => utility [patent_app_number] => 16/945302 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945302
Blockchain data storage based on shared nodes and error correction code Jul 30, 2020 Issued
Array ( [id] => 17698992 [patent_doc_number] => 11372716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Detecting special handling metadata using address verification [patent_app_type] => utility [patent_app_number] => 16/941022 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941022 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941022
Detecting special handling metadata using address verification Jul 27, 2020 Issued
Array ( [id] => 17492230 [patent_doc_number] => 11281533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Hybrid iterative error correcting and redundancy decoding operations for memory sub-systems [patent_app_type] => utility [patent_app_number] => 16/947311 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947311
Hybrid iterative error correcting and redundancy decoding operations for memory sub-systems Jul 27, 2020 Issued
Array ( [id] => 16439110 [patent_doc_number] => 20200356436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => MULTICHIP PACKAGE LINK ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 16/938842 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16938842 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/938842
Multichip package link error detection Jul 23, 2020 Issued
Array ( [id] => 17423111 [patent_doc_number] => 11256565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Transaction metadata [patent_app_type] => utility [patent_app_number] => 16/931787 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/931787
Transaction metadata Jul 16, 2020 Issued
Array ( [id] => 17819228 [patent_doc_number] => 11424856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Encoding and decoding source information using a distribution channel encoder and decoder [patent_app_type] => utility [patent_app_number] => 16/929477 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 10489 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929477
Encoding and decoding source information using a distribution channel encoder and decoder Jul 14, 2020 Issued
Array ( [id] => 17605936 [patent_doc_number] => 11334425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-17 [patent_title] => Transmitting synchronized data streams in a distributed storage network [patent_app_type] => utility [patent_app_number] => 16/921451 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7947 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921451 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921451
Transmitting synchronized data streams in a distributed storage network Jul 5, 2020 Issued
Array ( [id] => 17918750 [patent_doc_number] => 20220321146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => CODING PATTERN, CODING AND READING METHODS FOR SAME, CALIBRATION BOARD, AND CALIBRATION METHOD [patent_app_type] => utility [patent_app_number] => 17/624953 [patent_app_country] => US [patent_app_date] => 2020-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17624953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/624953
Coding pattern, coding and reading methods for same, calibration board, and calibration method Jul 3, 2020 Issued
Array ( [id] => 17153191 [patent_doc_number] => 11146290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Bit-flipping method for decoding LDPC code and system using the same [patent_app_type] => utility [patent_app_number] => 16/917961 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12419 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917961 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917961
Bit-flipping method for decoding LDPC code and system using the same Jun 30, 2020 Issued
Array ( [id] => 17254711 [patent_doc_number] => 11190219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Decoder for irregular error correcting codes [patent_app_type] => utility [patent_app_number] => 16/917870 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 10066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917870
Decoder for irregular error correcting codes Jun 29, 2020 Issued
Array ( [id] => 16586881 [patent_doc_number] => 20210021283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => Encoding And Decoding Method And Terminal [patent_app_type] => utility [patent_app_number] => 16/914775 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914775 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914775
Encoding and decoding method and terminal Jun 28, 2020 Issued
Array ( [id] => 18767461 [patent_doc_number] => 11817879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => FPGA-based rate-adaptive spatially-coupled LDPC codes for optical communications [patent_app_type] => utility [patent_app_number] => 17/621639 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9648 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17621639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/621639
FPGA-based rate-adaptive spatially-coupled LDPC codes for optical communications Jun 25, 2020 Issued
Array ( [id] => 17024161 [patent_doc_number] => 20210248032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => MEMORY SYSTEM, MEMORY CONTROLLER, AND METHOD FOR OPERATING MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/910774 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910774 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910774
Memory system, memory controller, and method for operating memory system Jun 23, 2020 Issued
Array ( [id] => 16363214 [patent_doc_number] => 20200319965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => HARD AND SOFT BIT DATA FROM SINGLE READ [patent_app_type] => utility [patent_app_number] => 16/907669 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16907669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/907669
Hard and soft bit data from single read Jun 21, 2020 Issued
Array ( [id] => 17301671 [patent_doc_number] => 20210397510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => Managing Open Blocks in Memory Systems [patent_app_type] => utility [patent_app_number] => 16/906712 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906712 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906712
Managing open blocks in memory systems Jun 18, 2020 Issued
Array ( [id] => 17254700 [patent_doc_number] => 11190208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Techniques for link partner error reporting [patent_app_type] => utility [patent_app_number] => 16/905200 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13391 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905200 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905200
Techniques for link partner error reporting Jun 17, 2020 Issued
Array ( [id] => 17699997 [patent_doc_number] => 11373729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Grown bad block management in a memory sub-system [patent_app_type] => utility [patent_app_number] => 16/903066 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903066
Grown bad block management in a memory sub-system Jun 15, 2020 Issued
Array ( [id] => 17544776 [patent_doc_number] => 11309917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Base parity-check matrices for LDPC codes that have subsets of orthogonal rows [patent_app_type] => utility [patent_app_number] => 16/901934 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901934
Base parity-check matrices for LDPC codes that have subsets of orthogonal rows Jun 14, 2020 Issued
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