Search

Samuel J. Walk

Examiner (ID: 6290)

Most Active Art Unit
2612
Art Unit(s)
2632, 2612
Total Applications
328
Issued Applications
222
Pending Applications
24
Abandoned Applications
82

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7631558 [patent_doc_number] => 06665779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Image backup method for backing up disk partitions of a storage device' [patent_app_type] => B1 [patent_app_number] => 09/329495 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5676 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665779.pdf [firstpage_image] =>[orig_patent_app_number] => 09329495 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329495
Image backup method for backing up disk partitions of a storage device Jun 9, 1999 Issued
Array ( [id] => 1509042 [patent_doc_number] => 06467032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Controlled reissue delay of memory requests to reduce shared memory address contention' [patent_app_type] => B1 [patent_app_number] => 09/325817 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 7138 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467032.pdf [firstpage_image] =>[orig_patent_app_number] => 09325817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325817
Controlled reissue delay of memory requests to reduce shared memory address contention Jun 3, 1999 Issued
Array ( [id] => 1385899 [patent_doc_number] => 06571319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'Methods and apparatus for combining a plurality of memory access transactions' [patent_app_type] => B2 [patent_app_number] => 09/325625 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2997 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571319.pdf [firstpage_image] =>[orig_patent_app_number] => 09325625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325625
Methods and apparatus for combining a plurality of memory access transactions Jun 3, 1999 Issued
Array ( [id] => 1444093 [patent_doc_number] => 06496910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method and device for loading instruction codes to a memory and linking said instruction codes' [patent_app_type] => B1 [patent_app_number] => 09/326175 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4257 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496910.pdf [firstpage_image] =>[orig_patent_app_number] => 09326175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326175
Method and device for loading instruction codes to a memory and linking said instruction codes Jun 3, 1999 Issued
Array ( [id] => 1540544 [patent_doc_number] => 06490653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system' [patent_app_type] => B1 [patent_app_number] => 09/325397 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3741 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490653.pdf [firstpage_image] =>[orig_patent_app_number] => 09325397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325397
Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system Jun 2, 1999 Issued
Array ( [id] => 1421006 [patent_doc_number] => 06542955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Microcontroller virtual memory system and method' [patent_app_type] => B1 [patent_app_number] => 09/325027 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5744 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542955.pdf [firstpage_image] =>[orig_patent_app_number] => 09325027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325027
Microcontroller virtual memory system and method Jun 2, 1999 Issued
Array ( [id] => 1567450 [patent_doc_number] => 06438672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Memory aliasing method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/327157 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7554 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438672.pdf [firstpage_image] =>[orig_patent_app_number] => 09327157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327157
Memory aliasing method and apparatus Jun 2, 1999 Issued
09/325069 METHOD AND APPARATUS FOR IMPROVING FILE SYSTEM RESPONSE TIME Jun 2, 1999 Abandoned
Array ( [id] => 1421117 [patent_doc_number] => 06542964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Cost-based optimization for content distribution using dynamic protocol selection and query resolution for cache server' [patent_app_type] => B1 [patent_app_number] => 09/324360 [patent_app_country] => US [patent_app_date] => 1999-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6102 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542964.pdf [firstpage_image] =>[orig_patent_app_number] => 09324360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/324360
Cost-based optimization for content distribution using dynamic protocol selection and query resolution for cache server Jun 1, 1999 Issued
Array ( [id] => 1524902 [patent_doc_number] => 06415366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method and apparatus for load distribution across memory banks with constrained access' [patent_app_type] => B1 [patent_app_number] => 09/324207 [patent_app_country] => US [patent_app_date] => 1999-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6228 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415366.pdf [firstpage_image] =>[orig_patent_app_number] => 09324207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/324207
Method and apparatus for load distribution across memory banks with constrained access Jun 1, 1999 Issued
Array ( [id] => 1513291 [patent_doc_number] => 06442664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Computer memory address translation system' [patent_app_type] => B1 [patent_app_number] => 09/323395 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3408 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442664.pdf [firstpage_image] =>[orig_patent_app_number] => 09323395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323395
Computer memory address translation system May 31, 1999 Issued
Array ( [id] => 1552969 [patent_doc_number] => 06446189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Computer system including a novel address translation mechanism' [patent_app_type] => B1 [patent_app_number] => 09/323321 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10810 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446189.pdf [firstpage_image] =>[orig_patent_app_number] => 09323321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323321
Computer system including a novel address translation mechanism May 31, 1999 Issued
Array ( [id] => 1604491 [patent_doc_number] => 06434677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and apparatus for altering data length to zero to maintain cache coherency' [patent_app_type] => B1 [patent_app_number] => 09/323360 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3072 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434677.pdf [firstpage_image] =>[orig_patent_app_number] => 09323360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323360
Method and apparatus for altering data length to zero to maintain cache coherency May 31, 1999 Issued
Array ( [id] => 1513298 [patent_doc_number] => 06442667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Selectively powering X Y organized memory banks' [patent_app_type] => B1 [patent_app_number] => 09/314557 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5015 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 717 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442667.pdf [firstpage_image] =>[orig_patent_app_number] => 09314557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314557
Selectively powering X Y organized memory banks May 18, 1999 Issued
Array ( [id] => 1540600 [patent_doc_number] => 06490672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method for computing a fast fourier transform and associated circuit for addressing a data memory' [patent_app_type] => B1 [patent_app_number] => 09/311964 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6675 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490672.pdf [firstpage_image] =>[orig_patent_app_number] => 09311964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311964
Method for computing a fast fourier transform and associated circuit for addressing a data memory May 13, 1999 Issued
Array ( [id] => 4346499 [patent_doc_number] => 06330653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Manipulation of virtual and live computer storage device partitions' [patent_app_type] => 1 [patent_app_number] => 9/302748 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 18639 [patent_no_of_claims] => 106 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330653.pdf [firstpage_image] =>[orig_patent_app_number] => 302748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302748
Manipulation of virtual and live computer storage device partitions Apr 29, 1999 Issued
Array ( [id] => 1431271 [patent_doc_number] => 06523105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Recording medium control device and method' [patent_app_type] => B1 [patent_app_number] => 09/202168 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9017 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523105.pdf [firstpage_image] =>[orig_patent_app_number] => 09202168 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/202168
Recording medium control device and method Apr 14, 1999 Issued
Array ( [id] => 1311219 [patent_doc_number] => 06625692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Integrated semiconductor memory chip with presence detect data capability' [patent_app_type] => B1 [patent_app_number] => 09/291369 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5569 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625692.pdf [firstpage_image] =>[orig_patent_app_number] => 09291369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291369
Integrated semiconductor memory chip with presence detect data capability Apr 13, 1999 Issued
Array ( [id] => 1416878 [patent_doc_number] => 06532517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'System and method for reducing disk chatter from disk-based data storage systems' [patent_app_type] => B1 [patent_app_number] => 09/291689 [patent_app_country] => US [patent_app_date] => 1999-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6280 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532517.pdf [firstpage_image] =>[orig_patent_app_number] => 09291689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291689
System and method for reducing disk chatter from disk-based data storage systems Apr 12, 1999 Issued
Array ( [id] => 1509033 [patent_doc_number] => 06467029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Data management apparatus and a data management method' [patent_app_type] => B1 [patent_app_number] => 09/288168 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6105 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467029.pdf [firstpage_image] =>[orig_patent_app_number] => 09288168 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/288168
Data management apparatus and a data management method Apr 7, 1999 Issued
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