Search

Samuel J. Walk

Examiner (ID: 6290)

Most Active Art Unit
2612
Art Unit(s)
2632, 2612
Total Applications
328
Issued Applications
222
Pending Applications
24
Abandoned Applications
82

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7391652 [patent_doc_number] => 20040083338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Disk array controller' [patent_app_type] => new [patent_app_number] => 10/341446 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5293 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083338.pdf [firstpage_image] =>[orig_patent_app_number] => 10341446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341446
Scalable disk array controller inter-connection network Jan 13, 2003 Issued
Array ( [id] => 7621152 [patent_doc_number] => 06978349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-20 [patent_title] => 'Adaptive cache memory management' [patent_app_type] => utility [patent_app_number] => 10/339206 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6335 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978349.pdf [firstpage_image] =>[orig_patent_app_number] => 10339206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339206
Adaptive cache memory management Jan 8, 2003 Issued
Array ( [id] => 7328702 [patent_doc_number] => 20040139295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Acceleration of input/output (I/O) communication through improved address translation' [patent_app_type] => new [patent_app_number] => 10/339766 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10680 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139295.pdf [firstpage_image] =>[orig_patent_app_number] => 10339766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339766
Acceleration of input/output (I/O) communication through improved address translation Jan 8, 2003 Issued
Array ( [id] => 7328676 [patent_doc_number] => 20040139287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Method, system, and computer program product for creating and managing memory affinity in logically partitioned data processing systems' [patent_app_type] => new [patent_app_number] => 10/339774 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4893 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139287.pdf [firstpage_image] =>[orig_patent_app_number] => 10339774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339774
Method, system, and computer program product for creating and managing memory affinity in logically partitioned data processing systems Jan 8, 2003 Issued
Array ( [id] => 947629 [patent_doc_number] => 06965964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Nand flash memory device' [patent_app_type] => utility [patent_app_number] => 10/340359 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5555 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965964.pdf [firstpage_image] =>[orig_patent_app_number] => 10340359 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/340359
Nand flash memory device Jan 8, 2003 Issued
Array ( [id] => 1004671 [patent_doc_number] => 06910110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Interleaving apparatus and method for a communication system' [patent_app_type] => utility [patent_app_number] => 10/338715 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5700 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910110.pdf [firstpage_image] =>[orig_patent_app_number] => 10338715 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338715
Interleaving apparatus and method for a communication system Jan 8, 2003 Issued
Array ( [id] => 981610 [patent_doc_number] => 06931497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Shared memory management utilizing a free list of buffer indices' [patent_app_type] => utility [patent_app_number] => 10/340078 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3857 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931497.pdf [firstpage_image] =>[orig_patent_app_number] => 10340078 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/340078
Shared memory management utilizing a free list of buffer indices Jan 8, 2003 Issued
Array ( [id] => 7293433 [patent_doc_number] => 20040111579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Apparatus and method for memory device block movement' [patent_app_type] => new [patent_app_number] => 10/338246 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2481 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20040111579.pdf [firstpage_image] =>[orig_patent_app_number] => 10338246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338246
Apparatus and method for memory device block movement Jan 7, 2003 Abandoned
Array ( [id] => 765162 [patent_doc_number] => 07017010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length' [patent_app_type] => utility [patent_app_number] => 10/338398 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8185 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017010.pdf [firstpage_image] =>[orig_patent_app_number] => 10338398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338398
Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length Jan 7, 2003 Issued
Array ( [id] => 950074 [patent_doc_number] => 06963957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Memory paging based on memory pressure and probability of use of pages' [patent_app_type] => utility [patent_app_number] => 10/337309 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4208 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963957.pdf [firstpage_image] =>[orig_patent_app_number] => 10337309 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337309
Memory paging based on memory pressure and probability of use of pages Jan 6, 2003 Issued
Array ( [id] => 999041 [patent_doc_number] => 06915393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Method and apparatus for physical memory partitioning' [patent_app_type] => utility [patent_app_number] => 10/337605 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3872 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915393.pdf [firstpage_image] =>[orig_patent_app_number] => 10337605 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337605
Method and apparatus for physical memory partitioning Jan 6, 2003 Issued
Array ( [id] => 6844504 [patent_doc_number] => 20030149851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Nonvolatile memory system' [patent_app_type] => new [patent_app_number] => 10/337314 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6902 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20030149851.pdf [firstpage_image] =>[orig_patent_app_number] => 10337314 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337314
Nonvolatile memory system Jan 6, 2003 Abandoned
Array ( [id] => 984628 [patent_doc_number] => 06928522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Unbalanced inclusive tags' [patent_app_type] => utility [patent_app_number] => 10/337607 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928522.pdf [firstpage_image] =>[orig_patent_app_number] => 10337607 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337607
Unbalanced inclusive tags Jan 6, 2003 Issued
Array ( [id] => 6836092 [patent_doc_number] => 20030163638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Information reproducing apparatus, data management information obtaining method, data management information obtaining program, and storage medium' [patent_app_type] => new [patent_app_number] => 10/337269 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7874 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163638.pdf [firstpage_image] =>[orig_patent_app_number] => 10337269 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337269
Information reproducing apparatus, data management information obtaining method, data management information obtaining program, and storage medium Jan 6, 2003 Issued
Array ( [id] => 771378 [patent_doc_number] => 07010666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-07 [patent_title] => 'Methods and apparatus for memory map generation on a programmable chip' [patent_app_type] => utility [patent_app_number] => 10/338784 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5974 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010666.pdf [firstpage_image] =>[orig_patent_app_number] => 10338784 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338784
Methods and apparatus for memory map generation on a programmable chip Jan 5, 2003 Issued
Array ( [id] => 1001732 [patent_doc_number] => 06912646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Storing and selecting multiple data streams in distributed memory devices' [patent_app_type] => utility [patent_app_number] => 10/337766 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4739 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912646.pdf [firstpage_image] =>[orig_patent_app_number] => 10337766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337766
Storing and selecting multiple data streams in distributed memory devices Jan 5, 2003 Issued
Array ( [id] => 1075133 [patent_doc_number] => 06839801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Deferred writing of data to be synchronized on magnetic tape employing a non-volatile store' [patent_app_type] => utility [patent_app_number] => 10/336694 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9612 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839801.pdf [firstpage_image] =>[orig_patent_app_number] => 10336694 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336694
Deferred writing of data to be synchronized on magnetic tape employing a non-volatile store Jan 5, 2003 Issued
Array ( [id] => 7331470 [patent_doc_number] => 20040131055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Memory management free pointer pool' [patent_app_type] => new [patent_app_number] => 10/337908 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4136 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20040131055.pdf [firstpage_image] =>[orig_patent_app_number] => 10337908 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337908
Memory management free pointer pool Jan 5, 2003 Abandoned
Array ( [id] => 7341401 [patent_doc_number] => 20040133762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'LINEAR ACCESS WINDOW' [patent_app_type] => new [patent_app_number] => 10/248285 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2916 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20040133762.pdf [firstpage_image] =>[orig_patent_app_number] => 10248285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248285
LINEAR ACCESS WINDOW Jan 5, 2003 Abandoned
Array ( [id] => 1112182 [patent_doc_number] => 06810473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Replacement algorithm for a replicated fully associative translation look-aside buffer' [patent_app_type] => B2 [patent_app_number] => 10/336708 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4360 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810473.pdf [firstpage_image] =>[orig_patent_app_number] => 10336708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336708
Replacement algorithm for a replicated fully associative translation look-aside buffer Jan 5, 2003 Issued
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