
Samuel S. Broda
Examiner (ID: 9530)
| Most Active Art Unit | 2123 |
| Art Unit(s) | OPLA, 2123, 2763 |
| Total Applications | 295 |
| Issued Applications | 224 |
| Pending Applications | 47 |
| Abandoned Applications | 23 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4291176
[patent_doc_number] => 06308302
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-23
[patent_title] => 'Semiconductor wiring technique for reducing electromigration'
[patent_app_type] => 1
[patent_app_number] => 8/944857
[patent_app_country] => US
[patent_app_date] => 1997-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/308/06308302.pdf
[firstpage_image] =>[orig_patent_app_number] => 944857
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/944857 | Semiconductor wiring technique for reducing electromigration | Oct 5, 1997 | Issued |
Array
(
[id] => 4423840
[patent_doc_number] => 06230116
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Apparatus and method for interacting with a simulated 3D interface to an operating system operative to control computer resources'
[patent_app_type] => 1
[patent_app_number] => 8/946106
[patent_app_country] => US
[patent_app_date] => 1997-10-02
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
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[pdf_file] => patents/06/230/06230116.pdf
[firstpage_image] =>[orig_patent_app_number] => 946106
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/946106 | Apparatus and method for interacting with a simulated 3D interface to an operating system operative to control computer resources | Oct 1, 1997 | Issued |
| 08/940037 | METHOD FOR COMMUNICATION INVOLVING MESSAGE FILES CREATED BY STANDARD-COMPLIANT EQUIPMENT | Oct 1, 1997 | Abandoned |
Array
(
[id] => 4064972
[patent_doc_number] => 06068661
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[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'Method of emulating synchronous communication'
[patent_app_type] => 1
[patent_app_number] => 8/942004
[patent_app_country] => US
[patent_app_date] => 1997-10-01
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[firstpage_image] =>[orig_patent_app_number] => 942004
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/942004 | Method of emulating synchronous communication | Sep 30, 1997 | Issued |
Array
(
[id] => 4205713
[patent_doc_number] => 06131079
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[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Method and device for automatic simulation verification'
[patent_app_type] => 1
[patent_app_number] => 8/941718
[patent_app_country] => US
[patent_app_date] => 1997-10-01
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Array
(
[id] => 4144309
[patent_doc_number] => 06106563
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[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Method and apparatus for extracting parameters for an electrical structure'
[patent_app_type] => 1
[patent_app_number] => 8/939117
[patent_app_country] => US
[patent_app_date] => 1997-09-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/939117 | Method and apparatus for extracting parameters for an electrical structure | Sep 25, 1997 | Issued |
Array
(
[id] => 4421051
[patent_doc_number] => 06173242
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[patent_issue_date] => 2001-01-09
[patent_title] => 'Circuit for simulating a break-over component'
[patent_app_type] => 1
[patent_app_number] => 8/937509
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/937509 | Circuit for simulating a break-over component | Sep 24, 1997 | Issued |
Array
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[id] => 4086560
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[patent_title] => 'Method for modelling three dimension objects and simulation of fluid flow'
[patent_app_type] => 1
[patent_app_number] => 8/932125
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[patent_app_date] => 1997-09-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/932125 | Method for modelling three dimension objects and simulation of fluid flow | Sep 16, 1997 | Issued |
Array
(
[id] => 3957546
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[patent_issue_date] => 1999-10-26
[patent_title] => 'Method of determining optimum product design parameters and system therefor'
[patent_app_type] => 1
[patent_app_number] => 8/927491
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Array
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[id] => 4016818
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[patent_title] => 'Framework for rules checking'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/922793 | Framework for rules checking | Sep 1, 1997 | Issued |
Array
(
[id] => 4226326
[patent_doc_number] => 06074427
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[patent_issue_date] => 2000-06-13
[patent_title] => 'Apparatus and method for simulating multiple nodes on a single machine'
[patent_app_type] => 1
[patent_app_number] => 8/919128
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/919128 | Apparatus and method for simulating multiple nodes on a single machine | Aug 29, 1997 | Issued |
Array
(
[id] => 4094256
[patent_doc_number] => 06066177
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[patent_issue_date] => 2000-05-23
[patent_title] => 'Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library'
[patent_app_type] => 1
[patent_app_number] => 8/917210
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/917210 | Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library | Aug 24, 1997 | Issued |
Array
(
[id] => 4037728
[patent_doc_number] => 05926631
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[patent_issue_date] => 1999-07-20
[patent_title] => 'Network computer emulator systems, methods and computer program products for personal computers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/911829 | Network computer emulator systems, methods and computer program products for personal computers | Aug 14, 1997 | Issued |
Array
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[patent_title] => 'Apparatus and method for performing model estimation utilizing a discriminant measure'
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Array
(
[id] => 4129475
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[patent_title] => 'Method of constructing testing procedures for analog circuits by using fault classification tables'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/904863 | Method of displaying logic simulation results and logic simulation support equipment | Jul 31, 1997 | Issued |
Array
(
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[patent_title] => 'Program-module substitution in a program loader for multiple-platform emulation'
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Array
(
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Array
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Array
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