Search

Samuel S. Broda

Examiner (ID: 9530)

Most Active Art Unit
2123
Art Unit(s)
OPLA, 2123, 2763
Total Applications
295
Issued Applications
224
Pending Applications
47
Abandoned Applications
23

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4291176 [patent_doc_number] => 06308302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Semiconductor wiring technique for reducing electromigration' [patent_app_type] => 1 [patent_app_number] => 8/944857 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3792 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308302.pdf [firstpage_image] =>[orig_patent_app_number] => 944857 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944857
Semiconductor wiring technique for reducing electromigration Oct 5, 1997 Issued
Array ( [id] => 4423840 [patent_doc_number] => 06230116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Apparatus and method for interacting with a simulated 3D interface to an operating system operative to control computer resources' [patent_app_type] => 1 [patent_app_number] => 8/946106 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 4803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230116.pdf [firstpage_image] =>[orig_patent_app_number] => 946106 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946106
Apparatus and method for interacting with a simulated 3D interface to an operating system operative to control computer resources Oct 1, 1997 Issued
08/940037 METHOD FOR COMMUNICATION INVOLVING MESSAGE FILES CREATED BY STANDARD-COMPLIANT EQUIPMENT Oct 1, 1997 Abandoned
Array ( [id] => 4064972 [patent_doc_number] => 06068661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Method of emulating synchronous communication' [patent_app_type] => 1 [patent_app_number] => 8/942004 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8604 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/068/06068661.pdf [firstpage_image] =>[orig_patent_app_number] => 942004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942004
Method of emulating synchronous communication Sep 30, 1997 Issued
Array ( [id] => 4205713 [patent_doc_number] => 06131079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Method and device for automatic simulation verification' [patent_app_type] => 1 [patent_app_number] => 8/941718 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6178 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131079.pdf [firstpage_image] =>[orig_patent_app_number] => 941718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941718
Method and device for automatic simulation verification Sep 30, 1997 Issued
Array ( [id] => 4144309 [patent_doc_number] => 06106563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method and apparatus for extracting parameters for an electrical structure' [patent_app_type] => 1 [patent_app_number] => 8/939117 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3033 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/106/06106563.pdf [firstpage_image] =>[orig_patent_app_number] => 939117 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939117
Method and apparatus for extracting parameters for an electrical structure Sep 25, 1997 Issued
Array ( [id] => 4421051 [patent_doc_number] => 06173242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Circuit for simulating a break-over component' [patent_app_type] => 1 [patent_app_number] => 8/937509 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4240 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173242.pdf [firstpage_image] =>[orig_patent_app_number] => 937509 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937509
Circuit for simulating a break-over component Sep 24, 1997 Issued
Array ( [id] => 4086560 [patent_doc_number] => 06096088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for modelling three dimension objects and simulation of fluid flow' [patent_app_type] => 1 [patent_app_number] => 8/932125 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7037 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096088.pdf [firstpage_image] =>[orig_patent_app_number] => 932125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932125
Method for modelling three dimension objects and simulation of fluid flow Sep 16, 1997 Issued
Array ( [id] => 3957546 [patent_doc_number] => 05974246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method of determining optimum product design parameters and system therefor' [patent_app_type] => 1 [patent_app_number] => 8/927491 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5036 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974246.pdf [firstpage_image] =>[orig_patent_app_number] => 927491 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927491
Method of determining optimum product design parameters and system therefor Sep 10, 1997 Issued
Array ( [id] => 4016818 [patent_doc_number] => 05987237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Framework for rules checking' [patent_app_type] => 1 [patent_app_number] => 8/922793 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4536 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987237.pdf [firstpage_image] =>[orig_patent_app_number] => 922793 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/922793
Framework for rules checking Sep 1, 1997 Issued
Array ( [id] => 4226326 [patent_doc_number] => 06074427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Apparatus and method for simulating multiple nodes on a single machine' [patent_app_type] => 1 [patent_app_number] => 8/919128 [patent_app_country] => US [patent_app_date] => 1997-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3795 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074427.pdf [firstpage_image] =>[orig_patent_app_number] => 919128 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919128
Apparatus and method for simulating multiple nodes on a single machine Aug 29, 1997 Issued
Array ( [id] => 4094256 [patent_doc_number] => 06066177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library' [patent_app_type] => 1 [patent_app_number] => 8/917210 [patent_app_country] => US [patent_app_date] => 1997-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 18428 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066177.pdf [firstpage_image] =>[orig_patent_app_number] => 917210 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917210
Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library Aug 24, 1997 Issued
Array ( [id] => 4037728 [patent_doc_number] => 05926631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Network computer emulator systems, methods and computer program products for personal computers' [patent_app_type] => 1 [patent_app_number] => 8/911829 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5850 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926631.pdf [firstpage_image] =>[orig_patent_app_number] => 911829 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911829
Network computer emulator systems, methods and computer program products for personal computers Aug 14, 1997 Issued
Array ( [id] => 4068748 [patent_doc_number] => 05970239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Apparatus and method for performing model estimation utilizing a discriminant measure' [patent_app_type] => 1 [patent_app_number] => 8/908120 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5060 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970239.pdf [firstpage_image] =>[orig_patent_app_number] => 908120 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908120
Apparatus and method for performing model estimation utilizing a discriminant measure Aug 10, 1997 Issued
Array ( [id] => 4129475 [patent_doc_number] => 06047114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method of constructing testing procedures for analog circuits by using fault classification tables' [patent_app_type] => 1 [patent_app_number] => 8/906088 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047114.pdf [firstpage_image] =>[orig_patent_app_number] => 906088 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906088
Method of constructing testing procedures for analog circuits by using fault classification tables Aug 4, 1997 Issued
Array ( [id] => 4145506 [patent_doc_number] => 06123734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of displaying logic simulation results and logic simulation support equipment' [patent_app_type] => 1 [patent_app_number] => 8/904863 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 10657 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/123/06123734.pdf [firstpage_image] =>[orig_patent_app_number] => 904863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904863
Method of displaying logic simulation results and logic simulation support equipment Jul 31, 1997 Issued
Array ( [id] => 1601484 [patent_doc_number] => 06385567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Program-module substitution in a program loader for multiple-platform emulation' [patent_app_type] => B1 [patent_app_number] => 08/904057 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3973 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385567.pdf [firstpage_image] =>[orig_patent_app_number] => 08904057 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904057
Program-module substitution in a program loader for multiple-platform emulation Jul 30, 1997 Issued
Array ( [id] => 4253708 [patent_doc_number] => 06081661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Command value decision unit' [patent_app_type] => 1 [patent_app_number] => 8/900467 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 38 [patent_no_of_words] => 9066 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081661.pdf [firstpage_image] =>[orig_patent_app_number] => 900467 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900467
Command value decision unit Jul 24, 1997 Issued
Array ( [id] => 4052648 [patent_doc_number] => 05995736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and system for automatically modelling registers for integrated circuit design' [patent_app_type] => 1 [patent_app_number] => 8/899521 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7222 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995736.pdf [firstpage_image] =>[orig_patent_app_number] => 899521 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/899521
Method and system for automatically modelling registers for integrated circuit design Jul 23, 1997 Issued
Array ( [id] => 4122620 [patent_doc_number] => 06120548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method and system for estimating particle motion' [patent_app_type] => 1 [patent_app_number] => 8/897728 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6498 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/120/06120548.pdf [firstpage_image] =>[orig_patent_app_number] => 897728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897728
Method and system for estimating particle motion Jul 20, 1997 Issued
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