Search

Samuel S. Broda

Examiner (ID: 9530)

Most Active Art Unit
2123
Art Unit(s)
OPLA, 2123, 2763
Total Applications
295
Issued Applications
224
Pending Applications
47
Abandoned Applications
23

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4205804 [patent_doc_number] => 06086617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'User directed heuristic design optimization search' [patent_app_type] => 1 [patent_app_number] => 8/898041 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 11156 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/086/06086617.pdf [firstpage_image] =>[orig_patent_app_number] => 898041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/898041
User directed heuristic design optimization search Jul 17, 1997 Issued
Array ( [id] => 4423857 [patent_doc_number] => 06230118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'DOS based application supports for a controllerless modem' [patent_app_type] => 1 [patent_app_number] => 8/885800 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 9404 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230118.pdf [firstpage_image] =>[orig_patent_app_number] => 885800 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885800
DOS based application supports for a controllerless modem Jun 29, 1997 Issued
Array ( [id] => 4137554 [patent_doc_number] => 06063130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Circuit simulation method' [patent_app_type] => 1 [patent_app_number] => 8/884264 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3661 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063130.pdf [firstpage_image] =>[orig_patent_app_number] => 884264 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884264
Circuit simulation method Jun 26, 1997 Issued
Array ( [id] => 4145739 [patent_doc_number] => 06128589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method and apparatus for modelling a system which includes the transmission and reception of signals' [patent_app_type] => 1 [patent_app_number] => 8/882453 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 8109 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128589.pdf [firstpage_image] =>[orig_patent_app_number] => 882453 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882453
Method and apparatus for modelling a system which includes the transmission and reception of signals Jun 25, 1997 Issued
Array ( [id] => 3968740 [patent_doc_number] => 05978584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Debugging apparatus for debugging a program by changing hardware environments without changing program operation state' [patent_app_type] => 1 [patent_app_number] => 8/878950 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 37 [patent_no_of_words] => 14027 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978584.pdf [firstpage_image] =>[orig_patent_app_number] => 878950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878950
Debugging apparatus for debugging a program by changing hardware environments without changing program operation state Jun 18, 1997 Issued
Array ( [id] => 4095602 [patent_doc_number] => 06051028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Digitiser' [patent_app_type] => 1 [patent_app_number] => 8/879016 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4475 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051028.pdf [firstpage_image] =>[orig_patent_app_number] => 879016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879016
Digitiser Jun 18, 1997 Issued
Array ( [id] => 4049168 [patent_doc_number] => 05943490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Distributed logic analyzer for use in a hardware logic emulation system' [patent_app_type] => 1 [patent_app_number] => 8/865657 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 42 [patent_no_of_words] => 22804 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943490.pdf [firstpage_image] =>[orig_patent_app_number] => 865657 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865657
Distributed logic analyzer for use in a hardware logic emulation system May 29, 1997 Issued
Array ( [id] => 4196924 [patent_doc_number] => 06021270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'System for generating geometry of object associated with one of similar products, based on geometrical characteristic of this one product' [patent_app_type] => 1 [patent_app_number] => 8/866349 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9188 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021270.pdf [firstpage_image] =>[orig_patent_app_number] => 866349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866349
System for generating geometry of object associated with one of similar products, based on geometrical characteristic of this one product May 29, 1997 Issued
Array ( [id] => 3965750 [patent_doc_number] => 05956500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method for incorporating boundary conditions into finite element analysis' [patent_app_type] => 1 [patent_app_number] => 8/866639 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4195 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956500.pdf [firstpage_image] =>[orig_patent_app_number] => 866639 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866639
Method for incorporating boundary conditions into finite element analysis May 29, 1997 Issued
Array ( [id] => 4002836 [patent_doc_number] => 05960191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Emulation system with time-multiplexed interconnect' [patent_app_type] => 1 [patent_app_number] => 8/865741 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 42 [patent_no_of_words] => 22803 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960191.pdf [firstpage_image] =>[orig_patent_app_number] => 865741 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865741
Emulation system with time-multiplexed interconnect May 29, 1997 Issued
Array ( [id] => 4379462 [patent_doc_number] => 06256600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Prediction and optimization method for homogeneous porous material and accoustical systems' [patent_app_type] => 1 [patent_app_number] => 8/858514 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 21622 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256600.pdf [firstpage_image] =>[orig_patent_app_number] => 858514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858514
Prediction and optimization method for homogeneous porous material and accoustical systems May 18, 1997 Issued
Array ( [id] => 3965519 [patent_doc_number] => 05991529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Testing of hardware by using a hardware system environment that mimics a virtual system environment' [patent_app_type] => 1 [patent_app_number] => 8/857154 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2499 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991529.pdf [firstpage_image] =>[orig_patent_app_number] => 857154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857154
Testing of hardware by using a hardware system environment that mimics a virtual system environment May 15, 1997 Issued
Array ( [id] => 4144903 [patent_doc_number] => 06102958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Multiresolutional decision support system' [patent_app_type] => 1 [patent_app_number] => 8/835539 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 15827 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/102/06102958.pdf [firstpage_image] =>[orig_patent_app_number] => 835539 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835539
Multiresolutional decision support system Apr 7, 1997 Issued
Array ( [id] => 4118751 [patent_doc_number] => 06023574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method for designing and manufacturing a suspension having optimized side profile' [patent_app_type] => 1 [patent_app_number] => 8/828339 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7196 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023574.pdf [firstpage_image] =>[orig_patent_app_number] => 828339 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/828339
Method for designing and manufacturing a suspension having optimized side profile Mar 27, 1997 Issued
Array ( [id] => 3974516 [patent_doc_number] => 05937182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Design verification system using expect buffers' [patent_app_type] => 1 [patent_app_number] => 8/829316 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4039 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937182.pdf [firstpage_image] =>[orig_patent_app_number] => 829316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829316
Design verification system using expect buffers Mar 26, 1997 Issued
Array ( [id] => 4081601 [patent_doc_number] => 06009259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Emulation System' [patent_app_type] => 1 [patent_app_number] => 8/821941 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7325 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009259.pdf [firstpage_image] =>[orig_patent_app_number] => 821941 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821941
Emulation System Mar 20, 1997 Issued
Array ( [id] => 4175344 [patent_doc_number] => 06157900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Knowledge based system and method for determining material properties from fabrication and operating parameters' [patent_app_type] => 1 [patent_app_number] => 8/818386 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157900.pdf [firstpage_image] =>[orig_patent_app_number] => 818386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/818386
Knowledge based system and method for determining material properties from fabrication and operating parameters Mar 13, 1997 Issued
Array ( [id] => 4002755 [patent_doc_number] => 05960188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method for modeling electrical interconnections in a cycle based simulator' [patent_app_type] => 1 [patent_app_number] => 8/816308 [patent_app_country] => US [patent_app_date] => 1997-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8960 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960188.pdf [firstpage_image] =>[orig_patent_app_number] => 816308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816308
Method for modeling electrical interconnections in a cycle based simulator Mar 12, 1997 Issued
Array ( [id] => 3928789 [patent_doc_number] => 06002854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method and apparatus for configuring systems' [patent_app_type] => 1 [patent_app_number] => 8/815399 [patent_app_country] => US [patent_app_date] => 1997-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15058 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002854.pdf [firstpage_image] =>[orig_patent_app_number] => 815399 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/815399
Method and apparatus for configuring systems Mar 9, 1997 Issued
Array ( [id] => 3965553 [patent_doc_number] => 05991531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Scalable width vector processor architecture for efficient emulation' [patent_app_type] => 1 [patent_app_number] => 8/804765 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10006 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991531.pdf [firstpage_image] =>[orig_patent_app_number] => 804765 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804765
Scalable width vector processor architecture for efficient emulation Feb 23, 1997 Issued
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