Search

Samuel S. Broda

Examiner (ID: 9530)

Most Active Art Unit
2123
Art Unit(s)
OPLA, 2123, 2763
Total Applications
295
Issued Applications
224
Pending Applications
47
Abandoned Applications
23

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1407151 [patent_doc_number] => 06556958 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Fast clustering with sparse data' [patent_app_type] => B1 [patent_app_number] => 09/298600 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7313 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556958.pdf [firstpage_image] =>[orig_patent_app_number] => 09298600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298600
Fast clustering with sparse data Apr 22, 1999 Issued
Array ( [id] => 1404608 [patent_doc_number] => 06560572 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Multi-simulator co-simulation' [patent_app_type] => B1 [patent_app_number] => 09/292012 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4838 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560572.pdf [firstpage_image] =>[orig_patent_app_number] => 09292012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292012
Multi-simulator co-simulation Apr 14, 1999 Issued
Array ( [id] => 1398754 [patent_doc_number] => 06564178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method and apparatus for evaluating processors for architectural compliance' [patent_app_type] => B1 [patent_app_number] => 09/290806 [patent_app_country] => US [patent_app_date] => 1999-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6748 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564178.pdf [firstpage_image] =>[orig_patent_app_number] => 09290806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290806
Method and apparatus for evaluating processors for architectural compliance Apr 12, 1999 Issued
Array ( [id] => 1404536 [patent_doc_number] => 06560568 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Deriving statistical device models from electrical test data' [patent_app_type] => B1 [patent_app_number] => 09/290321 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4821 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560568.pdf [firstpage_image] =>[orig_patent_app_number] => 09290321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290321
Deriving statistical device models from electrical test data Apr 11, 1999 Issued
Array ( [id] => 1422210 [patent_doc_number] => 06539345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Symbolic simulation using input space decomposition via Boolean functional representation in parametric form' [patent_app_type] => B1 [patent_app_number] => 09/289412 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4790 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539345.pdf [firstpage_image] =>[orig_patent_app_number] => 09289412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289412
Symbolic simulation using input space decomposition via Boolean functional representation in parametric form Apr 8, 1999 Issued
Array ( [id] => 1419832 [patent_doc_number] => 06542861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Simulation environment cache model apparatus and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/282618 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3037 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542861.pdf [firstpage_image] =>[orig_patent_app_number] => 09282618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282618
Simulation environment cache model apparatus and method therefor Mar 30, 1999 Issued
09/281771 ACOUSTIC RESPONSE SIMULATION SYSTEM Mar 29, 1999 Abandoned
Array ( [id] => 1297488 [patent_doc_number] => 06631344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation' [patent_app_type] => B1 [patent_app_number] => 09/277570 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5912 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631344.pdf [firstpage_image] =>[orig_patent_app_number] => 09277570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277570
Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation Mar 25, 1999 Issued
Array ( [id] => 1474439 [patent_doc_number] => 06408264 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Switch level simulation with cross-coupled devices' [patent_app_type] => B1 [patent_app_number] => 09/274211 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5410 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408264.pdf [firstpage_image] =>[orig_patent_app_number] => 09274211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274211
Switch level simulation with cross-coupled devices Mar 22, 1999 Issued
Array ( [id] => 7633245 [patent_doc_number] => 06658375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Compensation model and registration simulation apparatus and method for manufacturing of printed circuit boards' [patent_app_type] => B1 [patent_app_number] => 09/270303 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 45 [patent_no_of_words] => 20153 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658375.pdf [firstpage_image] =>[orig_patent_app_number] => 09270303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270303
Compensation model and registration simulation apparatus and method for manufacturing of printed circuit boards Mar 14, 1999 Issued
Array ( [id] => 1325012 [patent_doc_number] => 06615301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Integrated data transceiver circuit for use with a serial bus and bus interface' [patent_app_type] => B1 [patent_app_number] => 09/264502 [patent_app_country] => US [patent_app_date] => 1999-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 10603 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615301.pdf [firstpage_image] =>[orig_patent_app_number] => 09264502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/264502
Integrated data transceiver circuit for use with a serial bus and bus interface Mar 7, 1999 Issued
Array ( [id] => 1404521 [patent_doc_number] => 06560567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and apparatus for measuring on-wafer lumped capacitances in integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/262129 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6570 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560567.pdf [firstpage_image] =>[orig_patent_app_number] => 09262129 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262129
Method and apparatus for measuring on-wafer lumped capacitances in integrated circuits Mar 2, 1999 Issued
Array ( [id] => 1579810 [patent_doc_number] => 06470302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Interface device and method for interfacing instruments to vascular access simulation systems' [patent_app_type] => B1 [patent_app_number] => 09/238559 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7584 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470302.pdf [firstpage_image] =>[orig_patent_app_number] => 09238559 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238559
Interface device and method for interfacing instruments to vascular access simulation systems Jan 27, 1999 Issued
Array ( [id] => 1474442 [patent_doc_number] => 06408265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Metastability risk simulation analysis tool and method' [patent_app_type] => B1 [patent_app_number] => 09/233529 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3641 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408265.pdf [firstpage_image] =>[orig_patent_app_number] => 09233529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233529
Metastability risk simulation analysis tool and method Jan 19, 1999 Issued
Array ( [id] => 4402379 [patent_doc_number] => 06263299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Geometric aerial image simulation' [patent_app_type] => 1 [patent_app_number] => 9/234422 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 10032 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263299.pdf [firstpage_image] =>[orig_patent_app_number] => 234422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/234422
Geometric aerial image simulation Jan 18, 1999 Issued
Array ( [id] => 1501020 [patent_doc_number] => 06405156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for planning, constructing and/or maintaining a pipeline system and data processing system therefor' [patent_app_type] => B1 [patent_app_number] => 09/231502 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4730 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405156.pdf [firstpage_image] =>[orig_patent_app_number] => 09231502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231502
Method for planning, constructing and/or maintaining a pipeline system and data processing system therefor Jan 13, 1999 Issued
Array ( [id] => 4205739 [patent_doc_number] => 06131081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'System and method for digital simulation of an electrical circuit' [patent_app_type] => 1 [patent_app_number] => 9/212728 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 7088 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131081.pdf [firstpage_image] =>[orig_patent_app_number] => 212728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212728
System and method for digital simulation of an electrical circuit Dec 15, 1998 Issued
Array ( [id] => 1568390 [patent_doc_number] => 06339752 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Processor emulation instruction counter virtual memory address translation' [patent_app_type] => B1 [patent_app_number] => 09/212809 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 8687 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339752.pdf [firstpage_image] =>[orig_patent_app_number] => 09212809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212809
Processor emulation instruction counter virtual memory address translation Dec 14, 1998 Issued
Array ( [id] => 1526200 [patent_doc_number] => 06353806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'System level hardware simulator and its automation' [patent_app_type] => B1 [patent_app_number] => 09/197802 [patent_app_country] => US [patent_app_date] => 1998-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4943 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353806.pdf [firstpage_image] =>[orig_patent_app_number] => 09197802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/197802
System level hardware simulator and its automation Nov 22, 1998 Issued
Array ( [id] => 1512697 [patent_doc_number] => 06442515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Process model generation independent of application mode' [patent_app_type] => B1 [patent_app_number] => 09/195420 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9653 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442515.pdf [firstpage_image] =>[orig_patent_app_number] => 09195420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195420
Process model generation independent of application mode Nov 16, 1998 Issued
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