
Samuel S. Broda
Examiner (ID: 9530)
| Most Active Art Unit | 2123 |
| Art Unit(s) | OPLA, 2123, 2763 |
| Total Applications | 295 |
| Issued Applications | 224 |
| Pending Applications | 47 |
| Abandoned Applications | 23 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1407151
[patent_doc_number] => 06556958
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-29
[patent_title] => 'Fast clustering with sparse data'
[patent_app_type] => B1
[patent_app_number] => 09/298600
[patent_app_country] => US
[patent_app_date] => 1999-04-23
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/556/06556958.pdf
[firstpage_image] =>[orig_patent_app_number] => 09298600
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/298600 | Fast clustering with sparse data | Apr 22, 1999 | Issued |
Array
(
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[patent_doc_number] => 06560572
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Multi-simulator co-simulation'
[patent_app_type] => B1
[patent_app_number] => 09/292012
[patent_app_country] => US
[patent_app_date] => 1999-04-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/292012 | Multi-simulator co-simulation | Apr 14, 1999 | Issued |
Array
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[patent_doc_number] => 06564178
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[patent_issue_date] => 2003-05-13
[patent_title] => 'Method and apparatus for evaluating processors for architectural compliance'
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[patent_app_number] => 09/290806
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[patent_app_date] => 1999-04-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/290806 | Method and apparatus for evaluating processors for architectural compliance | Apr 12, 1999 | Issued |
Array
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[patent_doc_number] => 06560568
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[patent_issue_date] => 2003-05-06
[patent_title] => 'Deriving statistical device models from electrical test data'
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[patent_app_number] => 09/290321
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[patent_app_date] => 1999-04-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/290321 | Deriving statistical device models from electrical test data | Apr 11, 1999 | Issued |
Array
(
[id] => 1422210
[patent_doc_number] => 06539345
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[patent_issue_date] => 2003-03-25
[patent_title] => 'Symbolic simulation using input space decomposition via Boolean functional representation in parametric form'
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[patent_app_number] => 09/289412
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/289412 | Symbolic simulation using input space decomposition via Boolean functional representation in parametric form | Apr 8, 1999 | Issued |
Array
(
[id] => 1419832
[patent_doc_number] => 06542861
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[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'Simulation environment cache model apparatus and method therefor'
[patent_app_type] => B1
[patent_app_number] => 09/282618
[patent_app_country] => US
[patent_app_date] => 1999-03-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/282618 | Simulation environment cache model apparatus and method therefor | Mar 30, 1999 | Issued |
| 09/281771 | ACOUSTIC RESPONSE SIMULATION SYSTEM | Mar 29, 1999 | Abandoned |
Array
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[patent_title] => 'Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation'
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[patent_app_number] => 09/277570
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Array
(
[id] => 1474439
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[patent_issue_date] => 2002-06-18
[patent_title] => 'Switch level simulation with cross-coupled devices'
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[patent_app_number] => 09/274211
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/274211 | Switch level simulation with cross-coupled devices | Mar 22, 1999 | Issued |
Array
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[id] => 7633245
[patent_doc_number] => 06658375
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[patent_issue_date] => 2003-12-02
[patent_title] => 'Compensation model and registration simulation apparatus and method for manufacturing of printed circuit boards'
[patent_app_type] => B1
[patent_app_number] => 09/270303
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/270303 | Compensation model and registration simulation apparatus and method for manufacturing of printed circuit boards | Mar 14, 1999 | Issued |
Array
(
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[patent_doc_number] => 06615301
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[patent_issue_date] => 2003-09-02
[patent_title] => 'Integrated data transceiver circuit for use with a serial bus and bus interface'
[patent_app_type] => B1
[patent_app_number] => 09/264502
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/264502 | Integrated data transceiver circuit for use with a serial bus and bus interface | Mar 7, 1999 | Issued |
Array
(
[id] => 1404521
[patent_doc_number] => 06560567
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[patent_issue_date] => 2003-05-06
[patent_title] => 'Method and apparatus for measuring on-wafer lumped capacitances in integrated circuits'
[patent_app_type] => B1
[patent_app_number] => 09/262129
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/262129 | Method and apparatus for measuring on-wafer lumped capacitances in integrated circuits | Mar 2, 1999 | Issued |
Array
(
[id] => 1579810
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[patent_issue_date] => 2002-10-22
[patent_title] => 'Interface device and method for interfacing instruments to vascular access simulation systems'
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[patent_app_number] => 09/238559
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/238559 | Interface device and method for interfacing instruments to vascular access simulation systems | Jan 27, 1999 | Issued |
Array
(
[id] => 1474442
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[patent_title] => 'Metastability risk simulation analysis tool and method'
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Array
(
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[patent_title] => 'Geometric aerial image simulation'
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Array
(
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Array
(
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Array
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Array
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Array
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