
Samuel S. Broda
Examiner (ID: 9530)
| Most Active Art Unit | 2123 |
| Art Unit(s) | OPLA, 2123, 2763 |
| Total Applications | 295 |
| Issued Applications | 224 |
| Pending Applications | 47 |
| Abandoned Applications | 23 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1591736
[patent_doc_number] => 06360188
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Time-based modeling'
[patent_app_type] => B1
[patent_app_number] => 09/182101
[patent_app_country] => US
[patent_app_date] => 1998-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 34
[patent_no_of_words] => 14149
[patent_no_of_claims] => 87
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/360/06360188.pdf
[firstpage_image] =>[orig_patent_app_number] => 09182101
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182101 | Time-based modeling | Oct 26, 1998 | Issued |
Array
(
[id] => 4202276
[patent_doc_number] => 06161081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-12
[patent_title] => 'Simulation model for a digital system'
[patent_app_type] => 1
[patent_app_number] => 9/169327
[patent_app_country] => US
[patent_app_date] => 1998-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3137
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/161/06161081.pdf
[firstpage_image] =>[orig_patent_app_number] => 169327
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/169327 | Simulation model for a digital system | Oct 8, 1998 | Issued |
Array
(
[id] => 1489788
[patent_doc_number] => 06366878
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Circuit arrangement for in-circuit emulation of a microcontroller'
[patent_app_type] => B1
[patent_app_number] => 09/163626
[patent_app_country] => US
[patent_app_date] => 1998-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3506
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/366/06366878.pdf
[firstpage_image] =>[orig_patent_app_number] => 09163626
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163626 | Circuit arrangement for in-circuit emulation of a microcontroller | Sep 27, 1998 | Issued |
Array
(
[id] => 4426350
[patent_doc_number] => 06178392
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Method for combining the computer models of two surfaces in 3-D space'
[patent_app_type] => 1
[patent_app_number] => 9/158323
[patent_app_country] => US
[patent_app_date] => 1998-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4381
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/178/06178392.pdf
[firstpage_image] =>[orig_patent_app_number] => 158323
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/158323 | Method for combining the computer models of two surfaces in 3-D space | Sep 21, 1998 | Issued |
Array
(
[id] => 1568387
[patent_doc_number] => 06339751
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-15
[patent_title] => 'Circuit design support apparatus and a method'
[patent_app_type] => B1
[patent_app_number] => 09/153910
[patent_app_country] => US
[patent_app_date] => 1998-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 39
[patent_no_of_words] => 7921
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/339/06339751.pdf
[firstpage_image] =>[orig_patent_app_number] => 09153910
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153910 | Circuit design support apparatus and a method | Sep 15, 1998 | Issued |
Array
(
[id] => 1480354
[patent_doc_number] => 06389380
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'System and method for performing compound computational experiments'
[patent_app_type] => B1
[patent_app_number] => 09/154606
[patent_app_country] => US
[patent_app_date] => 1998-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 18250
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/389/06389380.pdf
[firstpage_image] =>[orig_patent_app_number] => 09154606
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/154606 | System and method for performing compound computational experiments | Sep 15, 1998 | Issued |
Array
(
[id] => 4258296
[patent_doc_number] => 06167364
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Methods and apparatus for automatically generating interconnect patterns in programmable logic devices'
[patent_app_type] => 1
[patent_app_number] => 9/153754
[patent_app_country] => US
[patent_app_date] => 1998-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 4042
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/167/06167364.pdf
[firstpage_image] =>[orig_patent_app_number] => 153754
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153754 | Methods and apparatus for automatically generating interconnect patterns in programmable logic devices | Sep 14, 1998 | Issued |
Array
(
[id] => 4350160
[patent_doc_number] => 06314388
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Design tool for predictively indicating edge conditions in metal slitting'
[patent_app_type] => 1
[patent_app_number] => 9/150523
[patent_app_country] => US
[patent_app_date] => 1998-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 9022
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314388.pdf
[firstpage_image] =>[orig_patent_app_number] => 150523
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/150523 | Design tool for predictively indicating edge conditions in metal slitting | Sep 9, 1998 | Issued |
Array
(
[id] => 4422254
[patent_doc_number] => 06311148
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'Method for determining static flip-flop setup and hold times'
[patent_app_type] => 1
[patent_app_number] => 9/150508
[patent_app_country] => US
[patent_app_date] => 1998-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5313
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/311/06311148.pdf
[firstpage_image] =>[orig_patent_app_number] => 150508
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/150508 | Method for determining static flip-flop setup and hold times | Sep 8, 1998 | Issued |
Array
(
[id] => 4156499
[patent_doc_number] => 06061510
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Local bus interface'
[patent_app_type] => 1
[patent_app_number] => 9/149689
[patent_app_country] => US
[patent_app_date] => 1998-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 4380
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/061/06061510.pdf
[firstpage_image] =>[orig_patent_app_number] => 149689
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/149689 | Local bus interface | Sep 7, 1998 | Issued |
Array
(
[id] => 4173720
[patent_doc_number] => 06108494
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Optimizing runtime communication processing between simulators'
[patent_app_type] => 1
[patent_app_number] => 9/139215
[patent_app_country] => US
[patent_app_date] => 1998-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 6994
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/108/06108494.pdf
[firstpage_image] =>[orig_patent_app_number] => 139215
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/139215 | Optimizing runtime communication processing between simulators | Aug 23, 1998 | Issued |
Array
(
[id] => 1481198
[patent_doc_number] => 06345240
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-05
[patent_title] => 'Device and method for parallel simulation task generation and distribution'
[patent_app_type] => B1
[patent_app_number] => 09/138702
[patent_app_country] => US
[patent_app_date] => 1998-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6269
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/345/06345240.pdf
[firstpage_image] =>[orig_patent_app_number] => 09138702
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/138702 | Device and method for parallel simulation task generation and distribution | Aug 23, 1998 | Issued |
Array
(
[id] => 4347833
[patent_doc_number] => 06321181
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Device and method for parallel simulation'
[patent_app_type] => 1
[patent_app_number] => 9/138701
[patent_app_country] => US
[patent_app_date] => 1998-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6332
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/321/06321181.pdf
[firstpage_image] =>[orig_patent_app_number] => 138701
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/138701 | Device and method for parallel simulation | Aug 23, 1998 | Issued |
Array
(
[id] => 965551
[patent_doc_number] => 06950790
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-27
[patent_title] => 'Method of processing seismic data'
[patent_app_type] => utility
[patent_app_number] => 09/463765
[patent_app_country] => US
[patent_app_date] => 1998-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3776
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/950/06950790.pdf
[firstpage_image] =>[orig_patent_app_number] => 09463765
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/463765 | Method of processing seismic data | Aug 11, 1998 | Issued |
Array
(
[id] => 4296932
[patent_doc_number] => 06282504
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Method of receiving a facsimile message'
[patent_app_type] => 1
[patent_app_number] => 9/128653
[patent_app_country] => US
[patent_app_date] => 1998-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6203
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/282/06282504.pdf
[firstpage_image] =>[orig_patent_app_number] => 128653
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/128653 | Method of receiving a facsimile message | Aug 3, 1998 | Issued |
Array
(
[id] => 4380480
[patent_doc_number] => 06192505
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Method and system for reducing state space variables prior to symbolic model checking'
[patent_app_type] => 1
[patent_app_number] => 9/124360
[patent_app_country] => US
[patent_app_date] => 1998-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2296
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/192/06192505.pdf
[firstpage_image] =>[orig_patent_app_number] => 124360
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/124360 | Method and system for reducing state space variables prior to symbolic model checking | Jul 28, 1998 | Issued |
Array
(
[id] => 4151643
[patent_doc_number] => 06122443
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Wire length minimization apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 9/122634
[patent_app_country] => US
[patent_app_date] => 1998-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 71
[patent_no_of_words] => 19364
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/122/06122443.pdf
[firstpage_image] =>[orig_patent_app_number] => 122634
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/122634 | Wire length minimization apparatus and method | Jul 26, 1998 | Issued |
Array
(
[id] => 4258240
[patent_doc_number] => 06167360
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Method and apparatus for dynamic optimization'
[patent_app_type] => 1
[patent_app_number] => 9/121949
[patent_app_country] => US
[patent_app_date] => 1998-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6599
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/167/06167360.pdf
[firstpage_image] =>[orig_patent_app_number] => 121949
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121949 | Method and apparatus for dynamic optimization | Jul 23, 1998 | Issued |
Array
(
[id] => 4314613
[patent_doc_number] => 06199032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Presenting an output signal generated by a receiving device in a simulated communication system'
[patent_app_type] => 1
[patent_app_number] => 9/120826
[patent_app_country] => US
[patent_app_date] => 1998-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5960
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/199/06199032.pdf
[firstpage_image] =>[orig_patent_app_number] => 120826
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120826 | Presenting an output signal generated by a receiving device in a simulated communication system | Jul 21, 1998 | Issued |
Array
(
[id] => 1556864
[patent_doc_number] => 06349271
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'Method and apparatus for simulating an oxidation process in a semiconductor device manufacturing step'
[patent_app_type] => B1
[patent_app_number] => 09/118928
[patent_app_country] => US
[patent_app_date] => 1998-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5786
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/349/06349271.pdf
[firstpage_image] =>[orig_patent_app_number] => 09118928
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/118928 | Method and apparatus for simulating an oxidation process in a semiconductor device manufacturing step | Jul 19, 1998 | Issued |