Search

Samuel S. Broda

Examiner (ID: 9530)

Most Active Art Unit
2123
Art Unit(s)
OPLA, 2123, 2763
Total Applications
295
Issued Applications
224
Pending Applications
47
Abandoned Applications
23

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1484420 [patent_doc_number] => 06453274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method of forming a pattern using proximity-effect-correction' [patent_app_type] => B2 [patent_app_number] => 09/116375 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 89 [patent_no_of_words] => 11586 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453274.pdf [firstpage_image] =>[orig_patent_app_number] => 09116375 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116375
Method of forming a pattern using proximity-effect-correction Jul 15, 1998 Issued
Array ( [id] => 4379432 [patent_doc_number] => 06256598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method and system for creating a control-flow structure which represents control logic, reconfigurable logic controller having the control logic, method for designing the controller and method for changing its control logic' [patent_app_type] => 1 [patent_app_number] => 9/114020 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 40 [patent_no_of_words] => 7396 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256598.pdf [firstpage_image] =>[orig_patent_app_number] => 114020 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114020
Method and system for creating a control-flow structure which represents control logic, reconfigurable logic controller having the control logic, method for designing the controller and method for changing its control logic Jul 9, 1998 Issued
Array ( [id] => 4422198 [patent_doc_number] => 06311143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Suiting apparatus and suiting method' [patent_app_type] => 1 [patent_app_number] => 9/101203 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8389 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311143.pdf [firstpage_image] =>[orig_patent_app_number] => 101203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/101203
Suiting apparatus and suiting method Jul 1, 1998 Issued
09/108406 COMPUTER SIMULATION METHOD FOR SEMICONDUCTOR DEVICE Jun 30, 1998 Abandoned
Array ( [id] => 4400443 [patent_doc_number] => 06278963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'System architecture for distribution of discrete-event simulations' [patent_app_type] => 1 [patent_app_number] => 9/108503 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 6182 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278963.pdf [firstpage_image] =>[orig_patent_app_number] => 108503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108503
System architecture for distribution of discrete-event simulations Jun 30, 1998 Issued
Array ( [id] => 4164421 [patent_doc_number] => 06083270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Devices and methods for interfacing human users with electronic devices' [patent_app_type] => 1 [patent_app_number] => 9/107807 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6843 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083270.pdf [firstpage_image] =>[orig_patent_app_number] => 107807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107807
Devices and methods for interfacing human users with electronic devices Jun 29, 1998 Issued
Array ( [id] => 4398609 [patent_doc_number] => 06304840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Fingerless glove for interacting with data processing system' [patent_app_type] => 1 [patent_app_number] => 9/107527 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2653 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304840.pdf [firstpage_image] =>[orig_patent_app_number] => 107527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107527
Fingerless glove for interacting with data processing system Jun 29, 1998 Issued
Array ( [id] => 1111942 [patent_doc_number] => 06810368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Mechanism for constructing predictive models that allow inputs to have missing values' [patent_app_type] => B1 [patent_app_number] => 09/106784 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810368.pdf [firstpage_image] =>[orig_patent_app_number] => 09106784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106784
Mechanism for constructing predictive models that allow inputs to have missing values Jun 28, 1998 Issued
Array ( [id] => 4347858 [patent_doc_number] => 06321183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Semiconductor device characteristic simulation apparatus and its method' [patent_app_type] => 1 [patent_app_number] => 9/103709 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4105 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321183.pdf [firstpage_image] =>[orig_patent_app_number] => 103709 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103709
Semiconductor device characteristic simulation apparatus and its method Jun 23, 1998 Issued
Array ( [id] => 1257910 [patent_doc_number] => 06671663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Time domain noise analysis' [patent_app_type] => B1 [patent_app_number] => 09/103704 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 6034 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671663.pdf [firstpage_image] =>[orig_patent_app_number] => 09103704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103704
Time domain noise analysis Jun 23, 1998 Issued
Array ( [id] => 4156512 [patent_doc_number] => 06061511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Reconstruction engine for a hardware circuit emulator' [patent_app_type] => 1 [patent_app_number] => 9/097138 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6926 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061511.pdf [firstpage_image] =>[orig_patent_app_number] => 097138 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097138
Reconstruction engine for a hardware circuit emulator Jun 11, 1998 Issued
Array ( [id] => 4323257 [patent_doc_number] => 06327557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method and system for creating electronic circuitry' [patent_app_type] => 1 [patent_app_number] => 9/090457 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 11100 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327557.pdf [firstpage_image] =>[orig_patent_app_number] => 090457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090457
Method and system for creating electronic circuitry Jun 3, 1998 Issued
Array ( [id] => 4377630 [patent_doc_number] => 06192327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Injection mold design system and injection mold design method' [patent_app_type] => 1 [patent_app_number] => 9/084965 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 96 [patent_figures_cnt] => 144 [patent_no_of_words] => 39706 [patent_no_of_claims] => 98 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192327.pdf [firstpage_image] =>[orig_patent_app_number] => 084965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084965
Injection mold design system and injection mold design method May 26, 1998 Issued
Array ( [id] => 1278520 [patent_doc_number] => 06654714 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method and system for selecting compatible processors to add to a multiprocessor computer' [patent_app_type] => B1 [patent_app_number] => 09/083959 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3483 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654714.pdf [firstpage_image] =>[orig_patent_app_number] => 09083959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083959
Method and system for selecting compatible processors to add to a multiprocessor computer May 21, 1998 Issued
Array ( [id] => 995633 [patent_doc_number] => 06917909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-12 [patent_title] => 'Facilitating guidance provision for an architectural exploration based design creation process' [patent_app_type] => utility [patent_app_number] => 09/080869 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9327 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917909.pdf [firstpage_image] =>[orig_patent_app_number] => 09080869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080869
Facilitating guidance provision for an architectural exploration based design creation process May 17, 1998 Issued
Array ( [id] => 4401237 [patent_doc_number] => 06305006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Generating candidate architectures for an architectural exploration based electronic design creation process' [patent_app_type] => 1 [patent_app_number] => 9/080868 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9218 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/305/06305006.pdf [firstpage_image] =>[orig_patent_app_number] => 080868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080868
Generating candidate architectures for an architectural exploration based electronic design creation process May 17, 1998 Issued
Array ( [id] => 4261291 [patent_doc_number] => 06167559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'FPGA structure having main, column and sector clock lines' [patent_app_type] => 1 [patent_app_number] => 9/078409 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11735 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167559.pdf [firstpage_image] =>[orig_patent_app_number] => 078409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/078409
FPGA structure having main, column and sector clock lines May 12, 1998 Issued
Array ( [id] => 4323634 [patent_doc_number] => 06253168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Generation of virtual combinatorial libraries of compounds' [patent_app_type] => 1 [patent_app_number] => 9/076405 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9167 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253168.pdf [firstpage_image] =>[orig_patent_app_number] => 076405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076405
Generation of virtual combinatorial libraries of compounds May 11, 1998 Issued
Array ( [id] => 4093106 [patent_doc_number] => 06099573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method and apparatus for modeling interactions' [patent_app_type] => 1 [patent_app_number] => 9/061973 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7891 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/099/06099573.pdf [firstpage_image] =>[orig_patent_app_number] => 061973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061973
Method and apparatus for modeling interactions Apr 16, 1998 Issued
Array ( [id] => 4222168 [patent_doc_number] => 06028989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Calculating crosstalk voltage from IC craftsman routing data' [patent_app_type] => 1 [patent_app_number] => 9/059220 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6790 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028989.pdf [firstpage_image] =>[orig_patent_app_number] => 059220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059220
Calculating crosstalk voltage from IC craftsman routing data Apr 12, 1998 Issued
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