Search

San M. Aung

Examiner (ID: 11298, Phone: (571)270-5792 , Office: P/3657 )

Most Active Art Unit
3657
Art Unit(s)
3616, 3657, 4165
Total Applications
1243
Issued Applications
936
Pending Applications
84
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18178093 [patent_doc_number] => 20230038822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => DUAL SILICIDE LAYERS IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/833607 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833607 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833607
Dual silicide layers in semiconductor devices Jun 5, 2022 Issued
Array ( [id] => 18821340 [patent_doc_number] => 20230395681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/832651 [patent_app_country] => US [patent_app_date] => 2022-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832651
Multi-gate device including semiconductor fin between dielectric fins and method of fabrication thereof Jun 4, 2022 Issued
Array ( [id] => 19421119 [patent_doc_number] => 20240297243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => Tunneling Field Effect Transistor and Manufacturing Method Thereof, Display Panel and Display Apparatus [patent_app_type] => utility [patent_app_number] => 18/026833 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18026833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/026833
Tunneling field effect transistor and manufacturing method thereof, display panel and display apparatus May 26, 2022 Issued
Array ( [id] => 18967455 [patent_doc_number] => 11901235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Ion implantation for nano-FET [patent_app_type] => utility [patent_app_number] => 17/824610 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 73 [patent_no_of_words] => 15345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824610
Ion implantation for nano-FET May 24, 2022 Issued
Array ( [id] => 20307125 [patent_doc_number] => 12453136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate [patent_app_type] => utility [patent_app_number] => 17/824812 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 1170 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824812
Method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate May 24, 2022 Issued
Array ( [id] => 17855182 [patent_doc_number] => 20220285225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => Integrated Circuit Device With Low Threshold Voltage [patent_app_type] => utility [patent_app_number] => 17/750579 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750579
Integrated circuit device with low threshold voltage May 22, 2022 Issued
Array ( [id] => 20332854 [patent_doc_number] => 12463139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Apparatus and method for fabricating multi-die interconnection using lithography process [patent_app_type] => utility [patent_app_number] => 17/746806 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 2680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746806
Apparatus and method for fabricating multi-die interconnection using lithography process May 16, 2022 Issued
Array ( [id] => 18161057 [patent_doc_number] => 20230027649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => DISPLAY APPARATUS INCLUDING DISPLAY MODULE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/745458 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745458
Display apparatus including display module with anisotropic conductive layer, front cover and side cover, and manufacturing method thereof May 15, 2022 Issued
Array ( [id] => 18548407 [patent_doc_number] => 11721769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Semiconductor device and display device including the same [patent_app_type] => utility [patent_app_number] => 17/743956 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 181 [patent_no_of_words] => 65636 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743956
Semiconductor device and display device including the same May 12, 2022 Issued
Array ( [id] => 17840694 [patent_doc_number] => 20220278000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Multi-Layered Insulating Film Stack [patent_app_type] => utility [patent_app_number] => 17/663321 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663321
Multi-layered insulating film stack May 12, 2022 Issued
Array ( [id] => 17833846 [patent_doc_number] => 20220271150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/743947 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743947 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743947
Method for manufacturing semiconductor device May 12, 2022 Issued
Array ( [id] => 18840162 [patent_doc_number] => 11848241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Semiconductor structure and related methods [patent_app_type] => utility [patent_app_number] => 17/662492 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 9207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662492
Semiconductor structure and related methods May 8, 2022 Issued
Array ( [id] => 18967456 [patent_doc_number] => 11901236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Semiconductor structure with gate-all-around devices and stacked FinFET devices [patent_app_type] => utility [patent_app_number] => 17/739925 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739925
Semiconductor structure with gate-all-around devices and stacked FinFET devices May 8, 2022 Issued
Array ( [id] => 18615543 [patent_doc_number] => 20230282280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/736409 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736409
Three-dimensional memory devices having a support stack comprising a sacrificial dielectric layer, and fabricating methods thereof May 3, 2022 Issued
Array ( [id] => 18669939 [patent_doc_number] => 11776851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/734521 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 8963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734521
Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof May 1, 2022 Issued
Array ( [id] => 18874879 [patent_doc_number] => 11862702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Gate-all-around integrated circuit structures having insulator FIN on insulator substrate [patent_app_type] => utility [patent_app_number] => 17/727603 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727603
Gate-all-around integrated circuit structures having insulator FIN on insulator substrate Apr 21, 2022 Issued
Array ( [id] => 17738144 [patent_doc_number] => 20220223606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/711448 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/711448
Memory device and method for forming the same Mar 31, 2022 Issued
Array ( [id] => 18857305 [patent_doc_number] => 11854900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/699920 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 7627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699920 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699920
Semiconductor device and method of forming the same Mar 20, 2022 Issued
Array ( [id] => 17700308 [patent_doc_number] => 11374042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-28 [patent_title] => 3D micro display semiconductor device and structure [patent_app_type] => utility [patent_app_number] => 17/699099 [patent_app_country] => US [patent_app_date] => 2022-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 108 [patent_no_of_words] => 18751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699099
3D micro display semiconductor device and structure Mar 18, 2022 Issued
Array ( [id] => 17708605 [patent_doc_number] => 20220208613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions [patent_app_type] => utility [patent_app_number] => 17/654626 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654626
FinFETs with epitaxy regions having mixed wavy and non-wavy portions Mar 13, 2022 Issued
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