Search

San Ming R Hui

Examiner (ID: 15529, Phone: (571)272-0626 , Office: P/1621 )

Most Active Art Unit
1617
Art Unit(s)
1627, 1621, 1628, 1629, 1617
Total Applications
2131
Issued Applications
956
Pending Applications
244
Abandoned Applications
931

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12061639 [patent_doc_number] => 20170337983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'FAST MAGNETOELECTRIC DEVICE BASED ON CURRENT-DRIVEN DOMAIN WALL PROPAGATION' [patent_app_type] => utility [patent_app_number] => 15/600958 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600958
Fast magnetoelectric device based on current-driven domain wall propagation May 21, 2017 Issued
Array ( [id] => 12155394 [patent_doc_number] => 20180026658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'LDPC DECODER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/599550 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14007 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599550 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599550
LDPC decoder, semiconductor memory system and operating method thereof May 18, 2017 Issued
Array ( [id] => 12691912 [patent_doc_number] => 20180122470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => NON-VOLATILE MEMORY, SYSTEM INCLUDING THE MEMORY AND METHOD FOR CONTROLLING THE MEMORY [patent_app_type] => utility [patent_app_number] => 15/598962 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598962 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598962
NON-VOLATILE MEMORY, SYSTEM INCLUDING THE MEMORY AND METHOD FOR CONTROLLING THE MEMORY May 17, 2017 Abandoned
Array ( [id] => 13018793 [patent_doc_number] => 10032511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-24 [patent_title] => Memory with dynamic permissible bit write logic and method [patent_app_type] => utility [patent_app_number] => 15/599350 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6654 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599350 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599350
Memory with dynamic permissible bit write logic and method May 17, 2017 Issued
Array ( [id] => 14903731 [patent_doc_number] => 20190295631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => METHOD AND APPARATUS FOR STORING AND ACCESSING MATRICES AND ARRAYS BY COLUMNS AND ROWS IN A PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 15/598322 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598322 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598322
Method and apparatus for storing and accessing matrices and arrays by columns and rows in a processing unit May 17, 2017 Issued
Array ( [id] => 13572459 [patent_doc_number] => 20180337777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => PHYSICAL UNCLONABLE FUNCTION CODE PROVIDING APPARATUS AND PROVIDING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/598293 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598293
Physical unclonable function code providing apparatus and providing method thereof May 16, 2017 Issued
Array ( [id] => 12188517 [patent_doc_number] => 20180047453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'LAYER-BASED MEMORY CONTROLLER OPTIMIZATIONS FOR THREE DIMENSIONAL MEMORY CONSTRUCTS' [patent_app_type] => utility [patent_app_number] => 15/589863 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589863
Layer-based memory controller optimizations for three dimensional memory constructs May 7, 2017 Issued
Array ( [id] => 13769013 [patent_doc_number] => 10176853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Pre-processing circuit with data-line DC immune clamping and associated method and sensing circuit [patent_app_type] => utility [patent_app_number] => 15/499876 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4619 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499876 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499876
Pre-processing circuit with data-line DC immune clamping and associated method and sensing circuit Apr 26, 2017 Issued
Array ( [id] => 13467421 [patent_doc_number] => 20180285253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => HYBRID DRAM ARRAY INCLUDING DISSIMILAR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 15/496936 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496936
Hybrid DRAM array including dissimilar memory cells Apr 24, 2017 Issued
Array ( [id] => 11855559 [patent_doc_number] => 20170230051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/494681 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7827 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15494681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/494681
Semiconductor device Apr 23, 2017 Issued
Array ( [id] => 15672449 [patent_doc_number] => 10600462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Bitcell state retention [patent_app_type] => utility [patent_app_number] => 15/495936 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 13163 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495936
Bitcell state retention Apr 23, 2017 Issued
Array ( [id] => 11839816 [patent_doc_number] => 20170221536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'METHODS AND APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 15/490327 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6828 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490327
Methods and apparatuses for modulating threshold voltages of memory cells Apr 17, 2017 Issued
Array ( [id] => 11840195 [patent_doc_number] => 20170221915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND CHANNELS AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/487920 [patent_app_country] => US [patent_app_date] => 2017-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 7571 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487920 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/487920
Non-volatile memory devices including vertical NAND channels and methods of forming the same Apr 13, 2017 Issued
Array ( [id] => 12188499 [patent_doc_number] => 20180047435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/481696 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481696 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481696
SEMICONDUCTOR DEVICE Apr 6, 2017 Abandoned
Array ( [id] => 12553461 [patent_doc_number] => 10014042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/481798 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5747 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481798 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481798
Semiconductor device Apr 6, 2017 Issued
Array ( [id] => 12375129 [patent_doc_number] => 09959935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Input-output circuit for supporting multiple-input shift register (MISR) function and memory device including the same [patent_app_type] => utility [patent_app_number] => 15/480724 [patent_app_country] => US [patent_app_date] => 2017-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8693 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15480724 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/480724
Input-output circuit for supporting multiple-input shift register (MISR) function and memory device including the same Apr 5, 2017 Issued
Array ( [id] => 12871834 [patent_doc_number] => 20180182453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => DATA MAPPING ENABLING FAST READ MULTI-LEVEL 3D NAND TO IMPROVE LIFETIME CAPACITY [patent_app_type] => utility [patent_app_number] => 15/472326 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472326 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472326
Data mapping enabling fast read multi-level 3D NAND to improve lifetime capacity Mar 28, 2017 Issued
Array ( [id] => 12456669 [patent_doc_number] => 09984759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-29 [patent_title] => Detecting data integrity in memory systems [patent_app_type] => utility [patent_app_number] => 15/471262 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 13459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471262 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471262
Detecting data integrity in memory systems Mar 27, 2017 Issued
Array ( [id] => 12334212 [patent_doc_number] => 09947404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Resistive memory apparatus, selective write circuit therefor, and operation method thereof [patent_app_type] => utility [patent_app_number] => 15/471326 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5190 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471326 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471326
Resistive memory apparatus, selective write circuit therefor, and operation method thereof Mar 27, 2017 Issued
Array ( [id] => 13056651 [patent_doc_number] => 10049721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-14 [patent_title] => Apparatuses and methods for in-memory operations [patent_app_type] => utility [patent_app_number] => 15/470516 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 30237 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470516 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470516
Apparatuses and methods for in-memory operations Mar 26, 2017 Issued
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