San Ming R Hui
Examiner (ID: 15529, Phone: (571)272-0626 , Office: P/1621 )
Most Active Art Unit | 1617 |
Art Unit(s) | 1627, 1621, 1628, 1629, 1617 |
Total Applications | 2131 |
Issued Applications | 956 |
Pending Applications | 244 |
Abandoned Applications | 931 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 13755073
[patent_doc_number] => 10170490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Memory device including pass transistors in memory tiers
[patent_app_type] => utility
[patent_app_number] => 15/450638
[patent_app_country] => US
[patent_app_date] => 2017-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 15777
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450638
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/450638 | Memory device including pass transistors in memory tiers | Mar 5, 2017 | Issued |
Array
(
[id] => 13018815
[patent_doc_number] => 10032523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-24
[patent_title] => Memory device including extra capacity and stacked memory device including the same
[patent_app_type] => utility
[patent_app_number] => 15/450588
[patent_app_country] => US
[patent_app_date] => 2017-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 10251
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450588
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/450588 | Memory device including extra capacity and stacked memory device including the same | Mar 5, 2017 | Issued |
Array
(
[id] => 12235864
[patent_doc_number] => 20180068727
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-08
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/449856
[patent_app_country] => US
[patent_app_date] => 2017-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 23514
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449856
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/449856 | Semiconductor memory device | Mar 2, 2017 | Issued |
Array
(
[id] => 12515541
[patent_doc_number] => 10002648
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-19
[patent_title] => Memory device, semiconductor device, and electronic device
[patent_app_type] => utility
[patent_app_number] => 15/447809
[patent_app_country] => US
[patent_app_date] => 2017-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 63
[patent_no_of_words] => 31173
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447809
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/447809 | Memory device, semiconductor device, and electronic device | Mar 1, 2017 | Issued |
Array
(
[id] => 12375120
[patent_doc_number] => 09959932
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-05-01
[patent_title] => Grouping memory cells into sub-blocks for program speed uniformity
[patent_app_type] => utility
[patent_app_number] => 15/437718
[patent_app_country] => US
[patent_app_date] => 2017-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 13153
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437718
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/437718 | Grouping memory cells into sub-blocks for program speed uniformity | Feb 20, 2017 | Issued |
Array
(
[id] => 12229644
[patent_doc_number] => 09916890
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-03-13
[patent_title] => 'Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells'
[patent_app_type] => utility
[patent_app_number] => 15/437482
[patent_app_country] => US
[patent_app_date] => 2017-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6055
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437482
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/437482 | Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells | Feb 20, 2017 | Issued |
Array
(
[id] => 11694177
[patent_doc_number] => 20170169894
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'DYNAMICALLY ADJUSTING READ VOLTAGE IN A NAND FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 15/424716
[patent_app_country] => US
[patent_app_date] => 2017-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4690
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424716
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/424716 | Dynamically adjusting read voltage in a NAND flash memory | Feb 2, 2017 | Issued |
Array
(
[id] => 13891309
[patent_doc_number] => 10198201
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-05
[patent_title] => Semiconductor apparatus, memory system and repair method thereof
[patent_app_type] => utility
[patent_app_number] => 15/416405
[patent_app_country] => US
[patent_app_date] => 2017-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2809
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15416405
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/416405 | Semiconductor apparatus, memory system and repair method thereof | Jan 25, 2017 | Issued |
Array
(
[id] => 11694176
[patent_doc_number] => 20170169893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'DYNAMICALLY ADJUSTING READ VOLTAGE IN A NAND FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 15/404739
[patent_app_country] => US
[patent_app_date] => 2017-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4715
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404739
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/404739 | Dynamically adjusting read voltage in a NAND flash memory | Jan 11, 2017 | Issued |
Array
(
[id] => 12435792
[patent_doc_number] => 09978446
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-22
[patent_title] => Memory with regulated ground nodes and method of retaining data therein
[patent_app_type] => utility
[patent_app_number] => 15/378821
[patent_app_country] => US
[patent_app_date] => 2016-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5889
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378821
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/378821 | Memory with regulated ground nodes and method of retaining data therein | Dec 13, 2016 | Issued |
Array
(
[id] => 11532769
[patent_doc_number] => 20170092748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-30
[patent_title] => 'VERTICAL BJT FOR HIGH DENSITY MEMORY'
[patent_app_type] => utility
[patent_app_number] => 15/371801
[patent_app_country] => US
[patent_app_date] => 2016-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3679
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15371801
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/371801 | Vertical BJT for high density memory | Dec 6, 2016 | Issued |
Array
(
[id] => 11693037
[patent_doc_number] => 20170168752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'NONVOLATILE MEMORY SYSTEM WITH ERASE SUSPEND CIRCUIT AND METHOD FOR ERASE SUSPEND MANAGEMENT'
[patent_app_type] => utility
[patent_app_number] => 15/370391
[patent_app_country] => US
[patent_app_date] => 2016-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7675
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370391
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/370391 | Nonvolatile memory system with erase suspend circuit and method for erase suspend management | Dec 5, 2016 | Issued |
Array
(
[id] => 11532372
[patent_doc_number] => 20170092350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-30
[patent_title] => 'METHOD, APPARATUS AND SYSTEM FOR RESPONDING TO A ROW HAMMER EVENT'
[patent_app_type] => utility
[patent_app_number] => 15/364123
[patent_app_country] => US
[patent_app_date] => 2016-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10108
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364123
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/364123 | Method, apparatus and system for responding to a row hammer event | Nov 28, 2016 | Issued |
Array
(
[id] => 11917364
[patent_doc_number] => 09785550
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-10-10
[patent_title] => 'Data storage device and operating method thereof'
[patent_app_type] => utility
[patent_app_number] => 15/363345
[patent_app_country] => US
[patent_app_date] => 2016-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5041
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363345
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/363345 | Data storage device and operating method thereof | Nov 28, 2016 | Issued |
Array
(
[id] => 11925374
[patent_doc_number] => 09792959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-17
[patent_title] => 'Data processing device'
[patent_app_type] => utility
[patent_app_number] => 15/351580
[patent_app_country] => US
[patent_app_date] => 2016-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 27
[patent_no_of_words] => 10996
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351580
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/351580 | Data processing device | Nov 14, 2016 | Issued |
Array
(
[id] => 14426769
[patent_doc_number] => 10318188
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-11
[patent_title] => Method of controlling memory cell access based on safe address mapping
[patent_app_type] => utility
[patent_app_number] => 15/345684
[patent_app_country] => US
[patent_app_date] => 2016-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 27
[patent_no_of_words] => 10785
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345684
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/345684 | Method of controlling memory cell access based on safe address mapping | Nov 7, 2016 | Issued |
Array
(
[id] => 12060668
[patent_doc_number] => 20170337012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'METHODS AND APPARATUSES OF COMPENSATING FOR DELAYS CAUSED BY AN EXTENSION LINE OF A STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/341620
[patent_app_country] => US
[patent_app_date] => 2016-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9621
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15341620
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/341620 | Methods and apparatuses of compensating for delays caused by an extension line of a storage device | Nov 1, 2016 | Issued |
Array
(
[id] => 14984565
[patent_doc_number] => 10446202
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-10-15
[patent_title] => Increasing error rate detection through distribution of read current load
[patent_app_type] => utility
[patent_app_number] => 15/338074
[patent_app_country] => US
[patent_app_date] => 2016-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 6962
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338074
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/338074 | Increasing error rate detection through distribution of read current load | Oct 27, 2016 | Issued |
Array
(
[id] => 16609040
[patent_doc_number] => 10910053
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-02
[patent_title] => Method of exchanging data with memory cells
[patent_app_type] => utility
[patent_app_number] => 15/780554
[patent_app_country] => US
[patent_app_date] => 2016-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1008
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15780554
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/780554 | Method of exchanging data with memory cells | Oct 20, 2016 | Issued |
Array
(
[id] => 14957081
[patent_doc_number] => 10439827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-08
[patent_title] => SRAM-based authentication circuit
[patent_app_type] => utility
[patent_app_number] => 15/288382
[patent_app_country] => US
[patent_app_date] => 2016-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8888
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288382
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/288382 | SRAM-based authentication circuit | Oct 6, 2016 | Issued |