Sana A. Al Hashemi

Array ( [id] => 16592900 [patent_doc_number] => 10902167 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-26 [patent_title] => Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits [patent_app_type] => utility [patent_app_number] => 16/506746 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16506746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15367815 [patent_doc_number] => 20200019672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING CELL REGION HAVING BOTH AA-CONTINUOUS AND AA-DISCONTINUOUS REGIONS, AND METHOD AND SYSTEM FOR GENERATING LAYOUT DIAGRAM OF SAME [patent_app_type] => utility [patent_app_number] => 16/506501 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16506501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16845054 [patent_doc_number] => 11017144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Form board merge [patent_app_type] => utility [patent_app_number] => 16/505181 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15710193 [patent_doc_number] => 20200101862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => CHARGING MANAGEMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/440805 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19079873 [patent_doc_number] => 11949257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Management device and power supply system [patent_app_type] => utility [patent_app_number] => 17/261058 [patent_app_country] => US [patent_app_date] => 2019-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9037 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16470586 [patent_doc_number] => 20200372123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => HARDWARE-SOFTWARE DESIGN FLOW FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES [patent_app_type] => utility [patent_app_number] => 16/421443 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16355531 [patent_doc_number] => 10796043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-06 [patent_title] => Non-adaptive pattern reordering to improve scan chain diagnostic resolution in circuit design and manufacture [patent_app_type] => utility [patent_app_number] => 16/419398 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7932 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16355538 [patent_doc_number] => 10796050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Method for generating aging model and manufacturing semiconductor chip using the same [patent_app_type] => utility [patent_app_number] => 16/416762 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17734103 [patent_doc_number] => 20220219562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => A METHOD FOR CONTROLLING CHARGING OF ELECTRICALLY DRIVEN VEHICLES, A COMPUTER PROGRAM, A COMPUTER READABLE MEDIUM, A CONTROL UNIT AND A BATTERY CHARGING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/612854 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17612854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16802405 [patent_doc_number] => 10997352 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => Routing congestion based on layer-assigned net and placement blockage [patent_app_type] => utility [patent_app_number] => 16/416008 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12524 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15151963 [patent_doc_number] => 20190354459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => METHOD AND APPARATUS FOR TRACING COMMON CAUSE FAILURE IN INTEGRATED DRAWING [patent_app_type] => utility [patent_app_number] => 16/414662 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16409077 [patent_doc_number] => 10817632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Integrated drawing producing method and apparatus for common cause tracing [patent_app_type] => utility [patent_app_number] => 16/414659 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3554 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15232281 [patent_doc_number] => 10503865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Methods and apparatus for automated design of semiconductor photonic devices [patent_app_type] => utility [patent_app_number] => 16/387729 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 17619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15059523 [patent_doc_number] => 10460068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Coupling aware wire capacitance adjust at global routing [patent_app_type] => utility [patent_app_number] => 16/384004 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18248326 [patent_doc_number] => 11604916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Method, system, and electronic device for detecting open/short circuit of PCB design layout [patent_app_type] => utility [patent_app_number] => 17/296230 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5736 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17296230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16346573 [patent_doc_number] => 20200311224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => MULTI-INSTANTIATION TIME BUDGETING FOR INTEGRATED CIRCUIT DESIGN AND MANUFACTURING [patent_app_type] => utility [patent_app_number] => 16/370008 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16371466 [patent_doc_number] => 10803228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-13 [patent_title] => System and method for implementing verification IP for pre-silicon functional verification of a layered protocol [patent_app_type] => utility [patent_app_number] => 16/370654 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8361 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14935747 [patent_doc_number] => 20190303511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Verifying a Hardware Design for a Component that Implements a Permutation Respecting Function [patent_app_type] => utility [patent_app_number] => 16/367493 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14585915 [patent_doc_number] => 20190220566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => DIE TO DIE INTERCONNECT STRUCTURE FOR MODULARIZED INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 16/368696 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16788305 [patent_doc_number] => 10990739 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Scan channel fabric for tiled circuit designs [patent_app_type] => utility [patent_app_number] => 16/366717 [patent_app_country] => US [patent_app_date] => 2019-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 16960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16366717 [rel_patent_id] =>[rel_patent_doc_number] =>)