Search

Sana A. Al Hashemi

Examiner (ID: 5836, Phone: (571)272-4013 , Office: P/2156 )

Most Active Art Unit
2156
Art Unit(s)
2169, 2161, 2156, 2162, 2165, 2164, 2171
Total Applications
1214
Issued Applications
976
Pending Applications
49
Abandoned Applications
194

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18856082 [patent_doc_number] => 11853666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-26 [patent_title] => Computer-aided design tool for wide-input logic initialization [patent_app_type] => utility [patent_app_number] => 17/503014 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 37360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/503014
Computer-aided design tool for wide-input logic initialization Oct 14, 2021 Issued
Array ( [id] => 19443362 [patent_doc_number] => 12093631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Method, system and verifying platform for system on chip verification [patent_app_type] => utility [patent_app_number] => 17/500768 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5446 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500768 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500768
Method, system and verifying platform for system on chip verification Oct 12, 2021 Issued
Array ( [id] => 18308024 [patent_doc_number] => 20230111924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => FUNCTIONAL-LEVEL PROCESSING COMPONENT FOR QUANTUM COMPUTERS [patent_app_type] => utility [patent_app_number] => 17/450584 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450584 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450584
Functional-level processing component for quantum computers Oct 11, 2021 Issued
Array ( [id] => 18766007 [patent_doc_number] => 11816409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-14 [patent_title] => Strongly connected component (SCC) graph representation for interactive analysis of overlapping loops in emulation and prototyping [patent_app_type] => utility [patent_app_number] => 17/498658 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498658 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498658
Strongly connected component (SCC) graph representation for interactive analysis of overlapping loops in emulation and prototyping Oct 10, 2021 Issued
Array ( [id] => 18750487 [patent_doc_number] => 11809801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-07 [patent_title] => Computer-aided design tool for circuit logic initialization [patent_app_type] => utility [patent_app_number] => 17/497554 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 36456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/497554
Computer-aided design tool for circuit logic initialization Oct 7, 2021 Issued
Array ( [id] => 18703635 [patent_doc_number] => 11790149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => System and method for tracing nets across multiple fabrics in an electronic design [patent_app_type] => utility [patent_app_number] => 17/496660 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 4872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496660
System and method for tracing nets across multiple fabrics in an electronic design Oct 6, 2021 Issued
Array ( [id] => 18881821 [patent_doc_number] => 20240005190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD, APPARATUS, TERMINAL AND STORAGE MEDIUM FOR QUANTUM TOPOLOGY GRAPH OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/029569 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18029569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/029569
Method, apparatus, terminal and storage medium for quantum topology graph optimization Sep 28, 2021 Issued
Array ( [id] => 18282626 [patent_doc_number] => 20230098098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SCALABLE SCRIBE REGIONS FOR IMPLEMENTING USER CIRCUIT DESIGNS IN AN INTEGRATED CIRCUIT USING DYNAMIC FUNCTION EXCHANGE [patent_app_type] => utility [patent_app_number] => 17/487781 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487781
Scalable scribe regions for implementing user circuit designs in an integrated circuit using dynamic function exchange Sep 27, 2021 Issued
Array ( [id] => 18293879 [patent_doc_number] => 20230103565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => REGISTER TRANSFER LEVEL NAVIGATION MICROSERVICES AND INSTRUMENTATION FOR CLOUD-NATIVE ELECTRONIC DESIGN AUTOMATION (EDA) PLATFORMS [patent_app_type] => utility [patent_app_number] => 17/487423 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487423
Register transfer level navigation microservices and instrumentation for cloud-native electronic design automation (EDA) platforms Sep 27, 2021 Issued
Array ( [id] => 18819118 [patent_doc_number] => 20230393458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => METHOD FOR GENERATING MASK PATTERN [patent_app_type] => utility [patent_app_number] => 18/031865 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18031865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/031865
METHOD FOR GENERATING MASK PATTERN Sep 26, 2021 Pending
Array ( [id] => 17508064 [patent_doc_number] => 20220101167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Hybrid Quantum Computation Architecture for Solving Quadratic Unconstrained Binary Optimization Problems [patent_app_type] => utility [patent_app_number] => 17/482288 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482288 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482288
Hybrid quantum computation architecture for solving quadratic unconstrained binary optimization problems Sep 21, 2021 Issued
Array ( [id] => 18204396 [patent_doc_number] => 11586791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-21 [patent_title] => Visualization of data buses in circuit designs [patent_app_type] => utility [patent_app_number] => 17/480389 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480389
Visualization of data buses in circuit designs Sep 20, 2021 Issued
Array ( [id] => 18766006 [patent_doc_number] => 11816408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-14 [patent_title] => Computer-aided design tool for majority or minority inverter graph synthesis [patent_app_type] => utility [patent_app_number] => 17/478688 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 36362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478688
Computer-aided design tool for majority or minority inverter graph synthesis Sep 16, 2021 Issued
Array ( [id] => 18950039 [patent_doc_number] => 11893335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-06 [patent_title] => System and method for routing in an electronic design [patent_app_type] => utility [patent_app_number] => 17/477855 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 4482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477855 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477855
System and method for routing in an electronic design Sep 16, 2021 Issued
Array ( [id] => 18227036 [patent_doc_number] => 20230066030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => CALIBRATION METHOD FOR EMULATING GROUP III-V SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING GROUP III-V SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/462747 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462747
Calibration method for emulating group III-V semiconductor device and method for manufacturing group III-V semiconductor device Aug 30, 2021 Issued
Array ( [id] => 18226848 [patent_doc_number] => 20230065842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => PREDICTION AND OPTIMIZATION OF MULTI-KERNEL CIRCUIT DESIGN PERFORMANCE USING A PROGRAMMABLE OVERLAY [patent_app_type] => utility [patent_app_number] => 17/411484 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411484
Prediction and optimization of multi-kernel circuit design performance using a programmable overlay Aug 24, 2021 Issued
Array ( [id] => 17751756 [patent_doc_number] => 20220229961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => Systems and Methods for Programming Electrical Fuse [patent_app_type] => utility [patent_app_number] => 17/411262 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411262
Systems and Methods for Programming Electrical Fuse Aug 24, 2021 Pending
Array ( [id] => 18547382 [patent_doc_number] => 11720735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Flat shell for an accelerator card [patent_app_type] => utility [patent_app_number] => 17/408218 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408218
Flat shell for an accelerator card Aug 19, 2021 Issued
Array ( [id] => 18330997 [patent_doc_number] => 11636243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Method and system for recording integrated circuit version [patent_app_type] => utility [patent_app_number] => 17/407378 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3174 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407378
Method and system for recording integrated circuit version Aug 19, 2021 Issued
Array ( [id] => 17886624 [patent_doc_number] => 20220302102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MODELING METHOD [patent_app_type] => utility [patent_app_number] => 17/403556 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403556
Modeling method Aug 15, 2021 Issued
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