Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17908389 [patent_doc_number] => 11462249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => System and method for reading and writing memory management data using a non-volatile cell based register [patent_app_type] => utility [patent_app_number] => 16/916612 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 16663 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916612
System and method for reading and writing memory management data using a non-volatile cell based register Jun 29, 2020 Issued
Array ( [id] => 17224492 [patent_doc_number] => 11177002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Programming memory cells using encoded TLC-fine [patent_app_type] => utility [patent_app_number] => 16/916285 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916285
Programming memory cells using encoded TLC-fine Jun 29, 2020 Issued
Array ( [id] => 16911204 [patent_doc_number] => 11043252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Semiconductor storage device, read method thereof, and test method thereof [patent_app_type] => utility [patent_app_number] => 16/916370 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 24014 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 522 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916370
Semiconductor storage device, read method thereof, and test method thereof Jun 29, 2020 Issued
Array ( [id] => 17318565 [patent_doc_number] => 20210407615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => MODIFIABLE REPAIR SOLUTIONS FOR A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/914927 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914927 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914927
Modifiable repair solutions for a memory array Jun 28, 2020 Issued
Array ( [id] => 16759569 [patent_doc_number] => 10978124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Method and circuits for programming STT-MRAM cells for reducing back-hopping [patent_app_type] => utility [patent_app_number] => 16/915126 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915126
Method and circuits for programming STT-MRAM cells for reducing back-hopping Jun 28, 2020 Issued
Array ( [id] => 17652465 [patent_doc_number] => 11355201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Leakage reduction circuit for read-only memory (ROM) structures [patent_app_type] => utility [patent_app_number] => 16/904983 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7543 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904983 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/904983
Leakage reduction circuit for read-only memory (ROM) structures Jun 17, 2020 Issued
Array ( [id] => 16973442 [patent_doc_number] => 11069421 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-20 [patent_title] => Circuitry for checking operation of error correction code (ECC) circuitry [patent_app_type] => utility [patent_app_number] => 16/902305 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902305
Circuitry for checking operation of error correction code (ECC) circuitry Jun 15, 2020 Issued
Array ( [id] => 16965981 [patent_doc_number] => 20210217480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING PAGE BUFFERS [patent_app_type] => utility [patent_app_number] => 16/897061 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897061 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/897061
Semiconductor memory device including page buffers Jun 8, 2020 Issued
Array ( [id] => 16904548 [patent_doc_number] => 20210183464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, A CONTROLLER, AND OPERATING METHODS OF THE SEMICONDUCTOR MEMORY DEVICE AND THE CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/889446 [patent_app_country] => US [patent_app_date] => 2020-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889446 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889446
Semiconductor memory device, a controller, and operating methods of the semiconductor memory device and the controller May 31, 2020 Issued
Array ( [id] => 16314704 [patent_doc_number] => 20200293442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => METHOD FOR MANAGING A MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/888836 [patent_app_country] => US [patent_app_date] => 2020-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888836 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/888836
Method for managing a memory apparatus May 30, 2020 Issued
Array ( [id] => 17152252 [patent_doc_number] => 11145339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Device and method for computing-in-memory [patent_app_type] => utility [patent_app_number] => 16/881380 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881380
Device and method for computing-in-memory May 21, 2020 Issued
Array ( [id] => 17469215 [patent_doc_number] => 11275692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Methods and apparatus for multi-banked victim cache with dual datapath [patent_app_type] => utility [patent_app_number] => 16/882241 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 54 [patent_no_of_words] => 95337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882241
Methods and apparatus for multi-banked victim cache with dual datapath May 21, 2020 Issued
Array ( [id] => 17283884 [patent_doc_number] => 11200924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Method of minimizing read-disturb-write effect of SRAM circuit and SRAM circuit thereof [patent_app_type] => utility [patent_app_number] => 16/876138 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876138 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876138
Method of minimizing read-disturb-write effect of SRAM circuit and SRAM circuit thereof May 17, 2020 Issued
Array ( [id] => 17152295 [patent_doc_number] => 11145382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Non-volatile memory with a well bias generation circuit [patent_app_type] => utility [patent_app_number] => 16/871320 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/871320
Non-volatile memory with a well bias generation circuit May 10, 2020 Issued
Array ( [id] => 16788968 [patent_doc_number] => 10991405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/868078 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6306 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868078
Semiconductor devices May 5, 2020 Issued
Array ( [id] => 16663365 [patent_doc_number] => 10932582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Multi-stage memory sensing [patent_app_type] => utility [patent_app_number] => 16/867420 [patent_app_country] => US [patent_app_date] => 2020-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867420 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/867420
Multi-stage memory sensing May 4, 2020 Issued
Array ( [id] => 17217508 [patent_doc_number] => 20210350846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => Associativity-Agnostic In-Cache Computing Memory Architecture Optimized for Multiplication [patent_app_type] => utility [patent_app_number] => 16/866570 [patent_app_country] => US [patent_app_date] => 2020-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866570 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866570
Associativity-agnostic in-cache computing memory architecture optimized for multiplication May 4, 2020 Issued
Array ( [id] => 17165953 [patent_doc_number] => 11152061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Systems and methods for writing and reading data stored in a polymer [patent_app_type] => utility [patent_app_number] => 16/866364 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 20337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866364 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866364
Systems and methods for writing and reading data stored in a polymer May 3, 2020 Issued
Array ( [id] => 18219325 [patent_doc_number] => 11594271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Memory cell driver, memory cell arrangement, and methods thereof [patent_app_type] => utility [patent_app_number] => 16/861640 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 14330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861640
Memory cell driver, memory cell arrangement, and methods thereof Apr 28, 2020 Issued
Array ( [id] => 17188512 [patent_doc_number] => 20210335397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => Configurable Multiplexing Circuitry [patent_app_type] => utility [patent_app_number] => 16/860764 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860764
Configurable multiplexing circuitry Apr 27, 2020 Issued
Menu