
Sang H. Nguyen
Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )
| Most Active Art Unit | 2877 |
| Art Unit(s) | 2877, 2886 |
| Total Applications | 2464 |
| Issued Applications | 2109 |
| Pending Applications | 129 |
| Abandoned Applications | 259 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16928062
[patent_doc_number] => 11049551
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-29
[patent_title] => Memory devices providing in situ computing using sequential transfer of row buffered data and related methods and circuits
[patent_app_type] => utility
[patent_app_number] => 16/682151
[patent_app_country] => US
[patent_app_date] => 2019-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7713
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682151
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/682151 | Memory devices providing in situ computing using sequential transfer of row buffered data and related methods and circuits | Nov 12, 2019 | Issued |
Array
(
[id] => 16810994
[patent_doc_number] => 20210133549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => CHARGE-SHARING COMPUTE-IN-MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/669855
[patent_app_country] => US
[patent_app_date] => 2019-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669855
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/669855 | Charge-sharing compute-in-memory system | Oct 30, 2019 | Issued |
Array
(
[id] => 16119187
[patent_doc_number] => 20200211616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/661342
[patent_app_country] => US
[patent_app_date] => 2019-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6193
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661342
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/661342 | Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus | Oct 22, 2019 | Issued |
Array
(
[id] => 16699683
[patent_doc_number] => 10950291
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-16
[patent_title] => Apparatuses and methods to perform duty cycle adjustment with back-bias voltage
[patent_app_type] => utility
[patent_app_number] => 16/661784
[patent_app_country] => US
[patent_app_date] => 2019-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9157
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661784
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/661784 | Apparatuses and methods to perform duty cycle adjustment with back-bias voltage | Oct 22, 2019 | Issued |
Array
(
[id] => 16179105
[patent_doc_number] => 20200226073
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => RANDOM CODE GENERATOR WITH NON-VOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/661012
[patent_app_country] => US
[patent_app_date] => 2019-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4890
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661012
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/661012 | Random code generator with non-volatile memory | Oct 22, 2019 | Issued |
Array
(
[id] => 17018193
[patent_doc_number] => 11087838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-10
[patent_title] => Voltage drivers with reduced power consumption during polarity transition
[patent_app_type] => utility
[patent_app_number] => 16/660594
[patent_app_country] => US
[patent_app_date] => 2019-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4215
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660594
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/660594 | Voltage drivers with reduced power consumption during polarity transition | Oct 21, 2019 | Issued |
Array
(
[id] => 17062901
[patent_doc_number] => 11107510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-31
[patent_title] => Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions
[patent_app_type] => utility
[patent_app_number] => 16/657445
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10779
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657445
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/657445 | Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions | Oct 17, 2019 | Issued |
Array
(
[id] => 15459225
[patent_doc_number] => 20200042437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-06
[patent_title] => METHOD FOR MANAGING A MEMORY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/596703
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14562
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596703
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/596703 | Method for managing a memory apparatus | Oct 7, 2019 | Issued |
Array
(
[id] => 15775209
[patent_doc_number] => 20200118622
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => LINEARLY WEIGHT UPDATABLE CMOS SYNAPTIC ARRAY WITHOUT CELL LOCATION DEPENDENCE
[patent_app_type] => utility
[patent_app_number] => 16/592334
[patent_app_country] => US
[patent_app_date] => 2019-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7054
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592334
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/592334 | Linearly weight updatable CMOS synaptic array without cell location dependence | Oct 2, 2019 | Issued |
Array
(
[id] => 16447975
[patent_doc_number] => 10839906
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-17
[patent_title] => In memory computing (IMC) memory circuit having 6T cells
[patent_app_type] => utility
[patent_app_number] => 16/588140
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 15021
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588140
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/588140 | In memory computing (IMC) memory circuit having 6T cells | Sep 29, 2019 | Issued |
Array
(
[id] => 16653148
[patent_doc_number] => 10930339
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-23
[patent_title] => Voltage bitline high (VBLH) regulation for computer memory
[patent_app_type] => utility
[patent_app_number] => 16/587496
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5892
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587496
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/587496 | Voltage bitline high (VBLH) regulation for computer memory | Sep 29, 2019 | Issued |
Array
(
[id] => 16684158
[patent_doc_number] => 10943647
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-09
[patent_title] => Bit-line mux driver with diode header for computer memory
[patent_app_type] => utility
[patent_app_number] => 16/587560
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6153
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587560
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/587560 | Bit-line mux driver with diode header for computer memory | Sep 29, 2019 | Issued |
Array
(
[id] => 16865619
[patent_doc_number] => 11024370
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Static random access memory with write assist adjustment
[patent_app_type] => utility
[patent_app_number] => 16/587504
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8994
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587504
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/587504 | Static random access memory with write assist adjustment | Sep 29, 2019 | Issued |
Array
(
[id] => 15351151
[patent_doc_number] => 20200013467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-09
[patent_title] => MEMORY DEVICE AND METHOD OF OPERATION
[patent_app_type] => utility
[patent_app_number] => 16/574669
[patent_app_country] => US
[patent_app_date] => 2019-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15582
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574669
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/574669 | Memory device and method of operation | Sep 17, 2019 | Issued |
Array
(
[id] => 16097923
[patent_doc_number] => 20200202948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/561454
[patent_app_country] => US
[patent_app_date] => 2019-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15304
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561454
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/561454 | Semiconductor memory device | Sep 4, 2019 | Issued |
Array
(
[id] => 17195874
[patent_doc_number] => 11164639
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-02
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 16/561094
[patent_app_country] => US
[patent_app_date] => 2019-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 31
[patent_no_of_words] => 20448
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561094
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/561094 | Semiconductor memory device | Sep 4, 2019 | Issued |
Array
(
[id] => 15839977
[patent_doc_number] => 20200135271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/560472
[patent_app_country] => US
[patent_app_date] => 2019-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13185
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560472
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/560472 | Semiconductor memory device | Sep 3, 2019 | Issued |
Array
(
[id] => 16536263
[patent_doc_number] => 10878876
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Apparatuses and methods for providing power for memory refresh operations
[patent_app_type] => utility
[patent_app_number] => 16/557948
[patent_app_country] => US
[patent_app_date] => 2019-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5195
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557948
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/557948 | Apparatuses and methods for providing power for memory refresh operations | Aug 29, 2019 | Issued |
Array
(
[id] => 16130103
[patent_doc_number] => 10698812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Updating cache using two bloom filters
[patent_app_type] => utility
[patent_app_number] => 16/550613
[patent_app_country] => US
[patent_app_date] => 2019-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6086
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550613
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/550613 | Updating cache using two bloom filters | Aug 25, 2019 | Issued |
Array
(
[id] => 15461469
[patent_doc_number] => 20200043559
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-06
[patent_title] => MANAGED NAND PERFORMANCE THROTTLING
[patent_app_type] => utility
[patent_app_number] => 16/542963
[patent_app_country] => US
[patent_app_date] => 2019-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22984
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542963
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/542963 | Managed NAND performance throttling | Aug 15, 2019 | Issued |