Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16958891 [patent_doc_number] => 11062768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Semiconductor memory apparatus, operation method of the semiconductor memory apparatus and system including the semiconductor memory apparatus [patent_app_type] => utility [patent_app_number] => 16/444446 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9476 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444446 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444446
Semiconductor memory apparatus, operation method of the semiconductor memory apparatus and system including the semiconductor memory apparatus Jun 17, 2019 Issued
Array ( [id] => 16528506 [patent_doc_number] => 20200402587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => NON-VOLATILE MEMORY ARRAY DRIVEN FROM BOTH SIDES FOR PERFORMANCE IMPROVEMENT [patent_app_type] => utility [patent_app_number] => 16/444410 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444410
Non-volatile memory array driven from both sides for performance improvement Jun 17, 2019 Issued
Array ( [id] => 16529535 [patent_doc_number] => 20200403616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING COMPLEMENTARY EXCLUSIVE OR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/444837 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444837
Computational memory cell and processing array device using complementary exclusive or memory cells Jun 17, 2019 Issued
Array ( [id] => 16943945 [patent_doc_number] => 11056193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Non-volatile memory devices having enhanced erase control circuits therein [patent_app_type] => utility [patent_app_number] => 16/442672 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16442672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/442672
Non-volatile memory devices having enhanced erase control circuits therein Jun 16, 2019 Issued
Array ( [id] => 14874725 [patent_doc_number] => 20190287604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => INTEGRATED CIRCUIT DEVICES CONFIGURED TO CONTROL DISCHARGE OF A CONTROL GATE VOLTAGE [patent_app_type] => utility [patent_app_number] => 16/430896 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430896
Integrated circuit devices configured to control discharge of a control gate voltage Jun 3, 2019 Issued
Array ( [id] => 17085267 [patent_doc_number] => 20210280274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => ACCESSING DATA STORAGE PROVIDED USING DOUBLE-STRANDED NUCLEIC ACID MOLECULES [patent_app_type] => utility [patent_app_number] => 17/261271 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/261271
Accessing data storage provided using double-stranded nucleic acid molecules May 28, 2019 Issued
Array ( [id] => 14811009 [patent_doc_number] => 20190272114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT [patent_app_type] => utility [patent_app_number] => 16/415714 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/415714
Apparatuses and methods for partitioned parallel data movement May 16, 2019 Issued
Array ( [id] => 16347766 [patent_doc_number] => 20200312417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD FOR PROGRAMMING IN NON-VOLATILE MEMORY DEVICE BY APPLYING MULTIPLE BITLINE BIAS VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/404744 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404744 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404744
Method for programming in non-volatile memory device by applying multiple bitline bias voltages May 6, 2019 Issued
Array ( [id] => 15872913 [patent_doc_number] => 20200143860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => PROTECTION CIRCUIT FOR MEMORY IN DISPLAY PANEL AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/398307 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16398307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/398307
Protection circuit for memory in display panel and display panel Apr 29, 2019 Issued
Array ( [id] => 14721925 [patent_doc_number] => 20190252026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => METHODS AND APPARATUSES INCLUDING AN ASYMMETRIC ASSIST DEVICE [patent_app_type] => utility [patent_app_number] => 16/397731 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397731 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397731
Methods and apparatuses including an asymmetric assist device Apr 28, 2019 Issued
Array ( [id] => 16707438 [patent_doc_number] => 10957380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Memory device scrambling address [patent_app_type] => utility [patent_app_number] => 16/369034 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369034 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369034
Memory device scrambling address Mar 28, 2019 Issued
Array ( [id] => 16943906 [patent_doc_number] => 11056154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/368868 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5701 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368868 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368868
Semiconductor memory device Mar 28, 2019 Issued
Array ( [id] => 15687545 [patent_doc_number] => 20200098436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING A NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/364588 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364588
Nonvolatile memory devices and methods of operating a nonvolatile memory Mar 25, 2019 Issued
Array ( [id] => 14937801 [patent_doc_number] => 20190304539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => IN-CELL DIFFERENTIAL READ-OUT CIRCUITRY FOR READING SIGNED WEIGHT VALUES IN RESISTIVE PROCESSING UNIT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/353111 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/353111
In-cell differential read-out circuitry for reading signed weight values in resistive processing unit architecture Mar 13, 2019 Issued
Array ( [id] => 14937799 [patent_doc_number] => 20190304538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => IN-CELL DIFFERENTIAL READ-OUT CIRCUITRY FOR READING SIGNED WEIGHT VALUES IN RESISTIVE PROCESSING UNIT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/352230 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352230 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352230
In-cell differential read-out circuitry for reading signed weight values in resistive processing unit architecture Mar 12, 2019 Issued
Array ( [id] => 14784365 [patent_doc_number] => 20190267080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Block Management for Dynamic Single-Level Cell Buffers in Storage Devices [patent_app_type] => utility [patent_app_number] => 16/288268 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288268 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/288268
Block management for dynamic single-level cell buffers in storage devices Feb 27, 2019 Issued
Array ( [id] => 16417600 [patent_doc_number] => 10825500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Data storage in synthetic antiferromagnets included in magnetic tunnel junctions [patent_app_type] => utility [patent_app_number] => 16/286793 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286793 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286793
Data storage in synthetic antiferromagnets included in magnetic tunnel junctions Feb 26, 2019 Issued
Array ( [id] => 14919943 [patent_doc_number] => 10431298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Nonvolatile memory and writing method [patent_app_type] => utility [patent_app_number] => 16/286056 [patent_app_country] => US [patent_app_date] => 2019-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 57 [patent_no_of_words] => 19386 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 749 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286056 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286056
Nonvolatile memory and writing method Feb 25, 2019 Issued
Array ( [id] => 14475133 [patent_doc_number] => 20190189213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/283239 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283239
Semiconductor storage device Feb 21, 2019 Issued
Array ( [id] => 14351159 [patent_doc_number] => 20190157552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => THREE-TERMINAL METASTABLE SYMMETRIC ZERO-VOLT BATTERY MEMRISTIVE DEVICE [patent_app_type] => utility [patent_app_number] => 16/241284 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241284
Three-terminal metastable symmetric zero-volt battery memristive device Jan 6, 2019 Issued
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