Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15611057 [patent_doc_number] => 10586595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Method and apparatus for reducing coupling between word lines and control gate lines in a flash memory system [patent_app_type] => utility [patent_app_number] => 16/118272 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 1781 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118272 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118272
Method and apparatus for reducing coupling between word lines and control gate lines in a flash memory system Aug 29, 2018 Issued
Array ( [id] => 15640809 [patent_doc_number] => 10593407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Fast programming methods for flash memory devices [patent_app_type] => utility [patent_app_number] => 16/117406 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3975 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117406
Fast programming methods for flash memory devices Aug 29, 2018 Issued
Array ( [id] => 14842621 [patent_doc_number] => 20190279711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/116718 [patent_app_country] => US [patent_app_date] => 2018-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116718 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116718
Semiconductor memory device Aug 28, 2018 Issued
Array ( [id] => 13908709 [patent_doc_number] => 20190043559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => TEMPERATURE MANAGEMENT IN OPEN-CHANNEL MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/116732 [patent_app_country] => US [patent_app_date] => 2018-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116732 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116732
Temperature management in open-channel memory devices Aug 28, 2018 Issued
Array ( [id] => 16339062 [patent_doc_number] => 10790029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Temperature compensation in memory sensing [patent_app_type] => utility [patent_app_number] => 16/111319 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10945 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111319 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/111319
Temperature compensation in memory sensing Aug 23, 2018 Issued
Array ( [id] => 13558469 [patent_doc_number] => 20180330782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => 2T-1R ARCHITECTURE FOR RESISTIVE RAM [patent_app_type] => utility [patent_app_number] => 16/043688 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043688
2T-1R architecture for resistive RAM Jul 23, 2018 Issued
Array ( [id] => 14457387 [patent_doc_number] => 10324654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Apparatuses and methods for partitioned parallel data movement [patent_app_type] => utility [patent_app_number] => 16/033471 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033471 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033471
Apparatuses and methods for partitioned parallel data movement Jul 11, 2018 Issued
Array ( [id] => 14475039 [patent_doc_number] => 20190189165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => REGULATOR, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/032672 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16032672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/032672
Regulator, memory system having the same, and operating method thereof Jul 10, 2018 Issued
Array ( [id] => 15984221 [patent_doc_number] => 10672445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Memory device including local support for target data searching and methods of operating the same [patent_app_type] => utility [patent_app_number] => 16/032768 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9562 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16032768 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/032768
Memory device including local support for target data searching and methods of operating the same Jul 10, 2018 Issued
Array ( [id] => 15369211 [patent_doc_number] => 20200020370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => DATA DEPENDENT KEEPER ON GLOBAL DATA LINES [patent_app_type] => utility [patent_app_number] => 16/031350 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031350
Data dependent keeper on global data lines Jul 9, 2018 Issued
Array ( [id] => 14954739 [patent_doc_number] => 10438646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-08 [patent_title] => Apparatuses and methods for providing power for memory refresh operations [patent_app_type] => utility [patent_app_number] => 16/027158 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5135 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16027158 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/027158
Apparatuses and methods for providing power for memory refresh operations Jul 2, 2018 Issued
Array ( [id] => 16339047 [patent_doc_number] => 10790013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-29 [patent_title] => Read-write architecture for low voltage SRAMs [patent_app_type] => utility [patent_app_number] => 16/026038 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 2774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026038 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/026038
Read-write architecture for low voltage SRAMs Jul 1, 2018 Issued
Array ( [id] => 14858763 [patent_doc_number] => 10418115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Managed NAND performance throttling [patent_app_type] => utility [patent_app_number] => 16/023926 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 22971 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16023926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/023926
Managed NAND performance throttling Jun 28, 2018 Issued
Array ( [id] => 15331083 [patent_doc_number] => 20200005871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/024002 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16024002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/024002
Concurrent programming of multiple cells for non-volatile memory devices Jun 28, 2018 Issued
Array ( [id] => 17047811 [patent_doc_number] => 11101001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Non-volatile memory with multi-plane mixed sub-block programming [patent_app_type] => utility [patent_app_number] => 16/021290 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 16934 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021290
Non-volatile memory with multi-plane mixed sub-block programming Jun 27, 2018 Issued
Array ( [id] => 17018204 [patent_doc_number] => 11087849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Non-volatile memory with bit line controlled multi-plane mixed sub-block programming [patent_app_type] => utility [patent_app_number] => 16/021282 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 16934 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021282 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021282
Non-volatile memory with bit line controlled multi-plane mixed sub-block programming Jun 27, 2018 Issued
Array ( [id] => 14984633 [patent_doc_number] => 10446236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-15 [patent_title] => Memory device and method of operation [patent_app_type] => utility [patent_app_number] => 16/021964 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 15559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021964 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021964
Memory device and method of operation Jun 27, 2018 Issued
Array ( [id] => 16928055 [patent_doc_number] => 11049544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Row hammer correction logic for dram with integrated processor [patent_app_type] => utility [patent_app_number] => 16/615636 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4934 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16615636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/615636
Row hammer correction logic for dram with integrated processor May 17, 2018 Issued
Array ( [id] => 16356238 [patent_doc_number] => 10796755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Permutation coding for improved memory cell operations [patent_app_type] => utility [patent_app_number] => 15/957098 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957098 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/957098
Permutation coding for improved memory cell operations Apr 18, 2018 Issued
Array ( [id] => 13513991 [patent_doc_number] => 20180308538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => MULTI-STAGE MEMORY SENSING [patent_app_type] => utility [patent_app_number] => 15/957742 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957742 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/957742
Multi-stage memory sensing Apr 18, 2018 Issued
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