Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14643977 [patent_doc_number] => 10366736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => MTP-Thyristor memory cell circuits and methods of operation [patent_app_type] => utility [patent_app_number] => 15/698447 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 12985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/698447
MTP-Thyristor memory cell circuits and methods of operation Sep 6, 2017 Issued
Array ( [id] => 12243023 [patent_doc_number] => 20180075886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'STORAGE DEVICE, METHOD FOR OPERATING STORAGE DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/695210 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13403 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695210 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695210
Storage device, method for operating storage device, semiconductor device, electronic component, and electronic device Sep 4, 2017 Issued
Array ( [id] => 13451351 [patent_doc_number] => 20180277218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/695470 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695470 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695470
Semiconductor storage device Sep 4, 2017 Issued
Array ( [id] => 13451307 [patent_doc_number] => 20180277196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY AND OUTPUT DRIVING CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 15/695830 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695830 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695830
Double data rate synchronous dynamic random access memory and output driving circuit thereof Sep 4, 2017 Issued
Array ( [id] => 13434697 [patent_doc_number] => 20180268891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/695866 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695866 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695866
Semiconductor memory device and memory system Sep 4, 2017 Issued
Array ( [id] => 13434709 [patent_doc_number] => 20180268897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/694952 [patent_app_country] => US [patent_app_date] => 2017-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694952 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694952
Semiconductor memory device Sep 3, 2017 Issued
Array ( [id] => 13666663 [patent_doc_number] => 10163504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Planar variable resistance memory [patent_app_type] => utility [patent_app_number] => 15/667000 [patent_app_country] => US [patent_app_date] => 2017-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 9474 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667000
Planar variable resistance memory Aug 1, 2017 Issued
Array ( [id] => 12054286 [patent_doc_number] => 20170330630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/667487 [patent_app_country] => US [patent_app_date] => 2017-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667487 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667487
Semiconductor device and control method of the semiconductor device Aug 1, 2017 Issued
Array ( [id] => 13845467 [patent_doc_number] => 20190026218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => UPDATING CACHE USING TWO BLOOM FILTERS [patent_app_type] => utility [patent_app_number] => 15/653776 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653776 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/653776
Updating cache using two bloom filters Jul 18, 2017 Issued
Array ( [id] => 11996254 [patent_doc_number] => 20170300409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'METHOD FOR MANAGING A MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/642295 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14848 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642295 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642295
Method for managing a memory apparatus Jul 4, 2017 Issued
Array ( [id] => 14616509 [patent_doc_number] => 10360958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Dual power rail cascode driver [patent_app_type] => utility [patent_app_number] => 15/617000 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9338 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617000
Dual power rail cascode driver Jun 7, 2017 Issued
Array ( [id] => 13201061 [patent_doc_number] => 10115450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-30 [patent_title] => Cascode complimentary dual level shifter [patent_app_type] => utility [patent_app_number] => 15/617020 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9542 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 840 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617020 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617020
Cascode complimentary dual level shifter Jun 7, 2017 Issued
Array ( [id] => 13613043 [patent_doc_number] => 20180358071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => Methods and Circuits for Programming STT-MRAM Cells for Reducing Back-Hopping [patent_app_type] => utility [patent_app_number] => 15/616116 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616116 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616116
Methods and circuits for programming STT-MRAM cells for reducing back-hopping Jun 6, 2017 Issued
Array ( [id] => 14332611 [patent_doc_number] => 10297330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Separate drain-side dummy word lines within a block to reduce program disturb [patent_app_type] => utility [patent_app_number] => 15/615972 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 42 [patent_no_of_words] => 18178 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615972
Separate drain-side dummy word lines within a block to reduce program disturb Jun 6, 2017 Issued
Array ( [id] => 14526351 [patent_doc_number] => 10340447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Three-terminal metastable symmetric zero-volt battery memristive device [patent_app_type] => utility [patent_app_number] => 15/616320 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5001 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616320
Three-terminal metastable symmetric zero-volt battery memristive device Jun 6, 2017 Issued
Array ( [id] => 11966823 [patent_doc_number] => 20170270976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'METHODS AND APPARATUSES FOR PROVIDING A PROGRAM VOLTAGE RESPONSIVE TO A VOLTAGE DETERMINATION' [patent_app_type] => utility [patent_app_number] => 15/610281 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/610281
Methods and apparatuses for providing a program voltage responsive to a voltage determination May 30, 2017 Issued
Array ( [id] => 15611027 [patent_doc_number] => 10586580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Magnetic tunnel junction element and magnetic memory [patent_app_type] => utility [patent_app_number] => 16/308166 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10970 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16308166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/308166
Magnetic tunnel junction element and magnetic memory May 18, 2017 Issued
Array ( [id] => 12141666 [patent_doc_number] => 20180019748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/596802 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19457 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596802
SEMICONDUCTOR DEVICE May 15, 2017 Abandoned
Array ( [id] => 12416274 [patent_doc_number] => 09972371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Memory device including memory cell for generating reference voltage [patent_app_type] => utility [patent_app_number] => 15/596558 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596558
Memory device including memory cell for generating reference voltage May 15, 2017 Issued
Array ( [id] => 12088912 [patent_doc_number] => 09842644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Memory device, operation method of the same, and operation method of memory controller' [patent_app_type] => utility [patent_app_number] => 15/596828 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596828
Memory device, operation method of the same, and operation method of memory controller May 15, 2017 Issued
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