Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11239719 [patent_doc_number] => 09466363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/369974 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 134 [patent_figures_cnt] => 138 [patent_no_of_words] => 33554 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14369974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/369974
Integrated circuit Dec 3, 2012 Issued
Array ( [id] => 10158349 [patent_doc_number] => 09190132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Reducing signal skew in memory and other devices' [patent_app_type] => utility [patent_app_number] => 13/676482 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13676482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/676482
Reducing signal skew in memory and other devices Nov 13, 2012 Issued
Array ( [id] => 9877217 [patent_doc_number] => 08964498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Systems and methods for reducing peak power consumption in a solid state drive controller' [patent_app_type] => utility [patent_app_number] => 13/676864 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 10261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13676864 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/676864
Systems and methods for reducing peak power consumption in a solid state drive controller Nov 13, 2012 Issued
Array ( [id] => 9750979 [patent_doc_number] => 08842465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Memory element and memory apparatus' [patent_app_type] => utility [patent_app_number] => 13/675328 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 11945 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675328
Memory element and memory apparatus Nov 12, 2012 Issued
Array ( [id] => 8890131 [patent_doc_number] => 20130163315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'MEMORY ELEMENT AND MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/675416 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11529 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675416 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675416
MEMORY ELEMENT AND MEMORY APPARATUS Nov 12, 2012 Abandoned
Array ( [id] => 10035223 [patent_doc_number] => 09076544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Operation for non-volatile storage system with shared bit lines' [patent_app_type] => utility [patent_app_number] => 13/674470 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 46 [patent_no_of_words] => 13687 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13674470 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/674470
Operation for non-volatile storage system with shared bit lines Nov 11, 2012 Issued
Array ( [id] => 10178984 [patent_doc_number] => 09209196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Memory circuit, method of driving the same, nonvolatile storage device using the same, and liquid crystal display device' [patent_app_type] => utility [patent_app_number] => 14/360686 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 20911 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14360686 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/360686
Memory circuit, method of driving the same, nonvolatile storage device using the same, and liquid crystal display device Nov 11, 2012 Issued
Array ( [id] => 10053295 [patent_doc_number] => 09093176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Power line lowering for write assisted control scheme' [patent_app_type] => utility [patent_app_number] => 13/674192 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5775 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13674192 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/674192
Power line lowering for write assisted control scheme Nov 11, 2012 Issued
Array ( [id] => 10531013 [patent_doc_number] => 09257152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Memory architectures having wiring structures that enable different access patterns in multiple dimensions' [patent_app_type] => utility [patent_app_number] => 13/673262 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 39 [patent_no_of_words] => 20915 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673262 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673262
Memory architectures having wiring structures that enable different access patterns in multiple dimensions Nov 8, 2012 Issued
Array ( [id] => 9475783 [patent_doc_number] => 20140133246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'CONFIGURABLE EMBEDDED MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/673892 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673892 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673892
Configurable embedded memory system Nov 8, 2012 Issued
Array ( [id] => 10839603 [patent_doc_number] => 08867288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Memory device and test method thereof' [patent_app_type] => utility [patent_app_number] => 13/672528 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4532 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672528 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672528
Memory device and test method thereof Nov 7, 2012 Issued
Array ( [id] => 10889450 [patent_doc_number] => 08913451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Memory device and test method thereof' [patent_app_type] => utility [patent_app_number] => 13/672577 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7201 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672577 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672577
Memory device and test method thereof Nov 7, 2012 Issued
Array ( [id] => 9461849 [patent_doc_number] => 20140126275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SYSTEM AND METHOD FOR TUNING A SUPPLY VOLTAGE FOR DATA RETENTION' [patent_app_type] => utility [patent_app_number] => 13/672616 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672616 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672616
System and method for tuning a supply voltage for data retention Nov 7, 2012 Issued
Array ( [id] => 8731809 [patent_doc_number] => 20130077378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/652957 [patent_app_country] => US [patent_app_date] => 2012-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5563 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652957 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/652957
Spin torque transfer memory cell structures and methods Oct 15, 2012 Issued
Array ( [id] => 8605240 [patent_doc_number] => 20130010551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'SYSTEMS, MEMORIES, AND METHODS FOR REPAIR IN OPEN DIGIT MEMORY ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 13/620018 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9107 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13620018 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/620018
Systems, memories, and methods for repair in open digit memory architectures Sep 13, 2012 Issued
Array ( [id] => 8583396 [patent_doc_number] => 20130002217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'LEVEL DETECTOR, INTERNAL VOLTAGE GENERATOR INCLUDING LEVEL DETECTOR, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING INTERNAL VOLTAGE GENERATOR' [patent_app_type] => utility [patent_app_number] => 13/612514 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9905 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13612514 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/612514
Level detector, internal voltage generator including level detector, and semiconductor memory device including internal voltage generator Sep 11, 2012 Issued
Array ( [id] => 10086065 [patent_doc_number] => 09123416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Non-volatile phase-change resistive memory' [patent_app_type] => utility [patent_app_number] => 14/343648 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 15289 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14343648 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/343648
Non-volatile phase-change resistive memory Sep 9, 2012 Issued
Array ( [id] => 8568645 [patent_doc_number] => 20120331216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/604644 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14472 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604644 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604644
Method for managing a memory apparatus, and associated memory apparatus thereof Sep 5, 2012 Issued
Array ( [id] => 8568692 [patent_doc_number] => 20120331263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'METHOD FOR MANAGING A MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/605977 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14352 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13605977 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/605977
Method for managing a memory apparatus Sep 5, 2012 Issued
Array ( [id] => 8568696 [patent_doc_number] => 20120331267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'METHOD FOR MANAGING A MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/604654 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14462 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604654 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604654
METHOD FOR MANAGING A MEMORY APPARATUS Sep 5, 2012 Abandoned
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