Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8975121 [patent_doc_number] => 20130208551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/508204 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13508204 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/508204
Semiconductor memory device and method for accessing the same Feb 27, 2012 Issued
Array ( [id] => 11300439 [patent_doc_number] => 09508448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Memory element and signal processing circuit' [patent_app_type] => utility [patent_app_number] => 13/405422 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 79 [patent_no_of_words] => 47089 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405422 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405422
Memory element and signal processing circuit Feb 26, 2012 Issued
Array ( [id] => 9168211 [patent_doc_number] => 08593895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Semiconductor device and control method thereof' [patent_app_type] => utility [patent_app_number] => 13/404940 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5926 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13404940 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/404940
Semiconductor device and control method thereof Feb 23, 2012 Issued
Array ( [id] => 8369419 [patent_doc_number] => 20120218802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'CONTENT ADDRESSABLE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/403398 [patent_app_country] => US [patent_app_date] => 2012-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 8965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13403398 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/403398
Content addressable memory Feb 22, 2012 Issued
Array ( [id] => 9002034 [patent_doc_number] => 20130223159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'MEMORY WITH VARIABLE STRENGTH SENSE AMPLIFIER' [patent_app_type] => utility [patent_app_number] => 13/403564 [patent_app_country] => US [patent_app_date] => 2012-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13403564 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/403564
Memory with variable strength sense amplifier Feb 22, 2012 Issued
Array ( [id] => 9577009 [patent_doc_number] => 08767436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Memory support provided with memory elements of ferroelectric material and non-destructive reading method thereof' [patent_app_type] => utility [patent_app_number] => 13/362478 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 6974 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362478 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/362478
Memory support provided with memory elements of ferroelectric material and non-destructive reading method thereof Jan 30, 2012 Issued
Array ( [id] => 8322683 [patent_doc_number] => 20120195094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'MEMORY SUPPORT PROVIDED WITH ELEMENTS OF FERROELECTRIC MATERIAL AND PROGRAMMING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/362434 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8482 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362434 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/362434
MEMORY SUPPORT PROVIDED WITH ELEMENTS OF FERROELECTRIC MATERIAL AND PROGRAMMING METHOD THEREOF Jan 30, 2012 Abandoned
Array ( [id] => 8565143 [patent_doc_number] => 20120327714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'Memory Architecture of 3D Array With Diode in Memory String' [patent_app_type] => utility [patent_app_number] => 13/363014 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13426 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13363014 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/363014
Memory Architecture of 3D Array With Diode in Memory String Jan 30, 2012 Abandoned
Array ( [id] => 8949085 [patent_doc_number] => 20130194865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'IMPLEMENTING ENHANCED DATA READ FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING' [patent_app_type] => utility [patent_app_number] => 13/361918 [patent_app_country] => US [patent_app_date] => 2012-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 7571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13361918 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/361918
Implementing enhanced data read for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding Jan 29, 2012 Issued
Array ( [id] => 8162584 [patent_doc_number] => 20120102296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Translation Lookaside Buffer (TLB) with Reserved Areas for Specific Sources' [patent_app_type] => utility [patent_app_number] => 13/338656 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7472 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102296.pdf [firstpage_image] =>[orig_patent_app_number] => 13338656 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/338656
Translation lookaside buffer (TLB) with reserved areas for specific sources Dec 27, 2011 Issued
Array ( [id] => 9456808 [patent_doc_number] => 08717825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Memory device and corresponding reading method' [patent_app_type] => utility [patent_app_number] => 13/331396 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8273 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331396 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331396
Memory device and corresponding reading method Dec 19, 2011 Issued
Array ( [id] => 9185384 [patent_doc_number] => 08625330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Nonvolatile memory apparatus and write control method thereof' [patent_app_type] => utility [patent_app_number] => 13/331196 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2552 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331196 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331196
Nonvolatile memory apparatus and write control method thereof Dec 19, 2011 Issued
Array ( [id] => 8250824 [patent_doc_number] => 20120155146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'RESISTANCE-CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/331229 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20120155146.pdf [firstpage_image] =>[orig_patent_app_number] => 13331229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331229
RESISTANCE-CHANGE MEMORY Dec 19, 2011 Abandoned
Array ( [id] => 8860023 [patent_doc_number] => 08462568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Command latency systems and methods' [patent_app_type] => utility [patent_app_number] => 13/331932 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331932 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331932
Command latency systems and methods Dec 19, 2011 Issued
Array ( [id] => 8882611 [patent_doc_number] => 20130155795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'Methodology for Recovering Failed Bit Cells in an Integrated Circuit Memory' [patent_app_type] => utility [patent_app_number] => 13/329580 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7334 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13329580 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/329580
Methodology for Recovering Failed Bit Cells in an Integrated Circuit Memory Dec 18, 2011 Abandoned
Array ( [id] => 9240715 [patent_doc_number] => 08605512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Nonvolatile semiconductor memory device and method of operating a nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/329372 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16663 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13329372 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/329372
Nonvolatile semiconductor memory device and method of operating a nonvolatile memory device Dec 18, 2011 Issued
Array ( [id] => 8766265 [patent_doc_number] => 20130094302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'INTEGRATED CIRCUIT CHIP AND SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/329688 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5928 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13329688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/329688
Integrated circuit chip and semiconductor memory device Dec 18, 2011 Issued
Array ( [id] => 8886431 [patent_doc_number] => 20130159615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'DDR RECEIVER ENABLE CYCLE TRAINING' [patent_app_type] => utility [patent_app_number] => 13/330518 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6841 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330518 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330518
DDR receiver enable cycle training Dec 18, 2011 Issued
Array ( [id] => 9966325 [patent_doc_number] => 09013949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Memory access control system and method' [patent_app_type] => utility [patent_app_number] => 13/330172 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9701 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330172 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330172
Memory access control system and method Dec 18, 2011 Issued
Array ( [id] => 8882613 [patent_doc_number] => 20130155797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'USING A PRECHARGE CHARACTERISTICS OF A NODE TO VALIDATE A PREVIOUS DATA/SIGNAL VALUE REPRESENTED BY A DISCHARGE OF SAID NODE' [patent_app_type] => utility [patent_app_number] => 13/328007 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5288 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13328007 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/328007
Using a precharge characteristics of a node to validate a previous data/signal value represented by a discharge of said node Dec 15, 2011 Issued
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