Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7566203 [patent_doc_number] => 20110286266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'MEMORY SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/107206 [patent_app_country] => US [patent_app_date] => 2011-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8811 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20110286266.pdf [firstpage_image] =>[orig_patent_app_number] => 13107206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/107206
Memory semiconductor device and method of operating the same May 12, 2011 Issued
Array ( [id] => 7585576 [patent_doc_number] => 20110280086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/105970 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20110280086.pdf [firstpage_image] =>[orig_patent_app_number] => 13105970 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105970
Semiconductor memory device and semiconductor memory system May 11, 2011 Issued
Array ( [id] => 8488311 [patent_doc_number] => 20120287718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'PROGRAMMING MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 13/106118 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3944 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13106118 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/106118
Programming memory cells May 11, 2011 Issued
Array ( [id] => 9301000 [patent_doc_number] => 08649236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Circuit and method for controlling leakage current in random access memory devices' [patent_app_type] => utility [patent_app_number] => 13/105274 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3401 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13105274 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105274
Circuit and method for controlling leakage current in random access memory devices May 10, 2011 Issued
Array ( [id] => 7655830 [patent_doc_number] => 20110305099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM' [patent_app_type] => utility [patent_app_number] => 13/105806 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0305/20110305099.pdf [firstpage_image] =>[orig_patent_app_number] => 13105806 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105806
HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM May 10, 2011 Abandoned
Array ( [id] => 9470777 [patent_doc_number] => 08724420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'SRAM write assist apparatus' [patent_app_type] => utility [patent_app_number] => 13/105382 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4387 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13105382 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105382
SRAM write assist apparatus May 10, 2011 Issued
Array ( [id] => 10833102 [patent_doc_number] => 08861281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Method of programming memory and memory apparatus utilizing the method' [patent_app_type] => utility [patent_app_number] => 13/105276 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9015 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13105276 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105276
Method of programming memory and memory apparatus utilizing the method May 10, 2011 Issued
Array ( [id] => 8488316 [patent_doc_number] => 20120287723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'METHOD AND CIRCUIT TO DISCHARGE BIT LINES AFTER AN ERASE PULSE' [patent_app_type] => utility [patent_app_number] => 13/104722 [patent_app_country] => US [patent_app_date] => 2011-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7113 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13104722 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/104722
Method and circuit to discharge bit lines after an erase pulse May 9, 2011 Issued
Array ( [id] => 5957724 [patent_doc_number] => 20110182111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'ELECTROMECHANICAL SWITCH AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/082605 [patent_app_country] => US [patent_app_date] => 2011-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 8547 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20110182111.pdf [firstpage_image] =>[orig_patent_app_number] => 13082605 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082605
Electromechanical switch and method of forming the same Apr 7, 2011 Issued
Array ( [id] => 7697985 [patent_doc_number] => 20110228605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/050418 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20110228605.pdf [firstpage_image] =>[orig_patent_app_number] => 13050418 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050418
NONVOLATILE MEMORY Mar 16, 2011 Abandoned
Array ( [id] => 8847756 [patent_doc_number] => 08456947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Integrated circuitry, switches, and methods of selecting memory cells of a memory device' [patent_app_type] => utility [patent_app_number] => 13/050630 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6942 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13050630 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050630
Integrated circuitry, switches, and methods of selecting memory cells of a memory device Mar 16, 2011 Issued
Array ( [id] => 8169454 [patent_doc_number] => 20120106258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'READOUT CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/050060 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20120106258.pdf [firstpage_image] =>[orig_patent_app_number] => 13050060 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050060
Readout circuit and semiconductor storage device Mar 16, 2011 Issued
Array ( [id] => 8404588 [patent_doc_number] => 20120236649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'HOT CARRIER PROGRAMMING OF NAND FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 13/050658 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6033 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13050658 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050658
HOT CARRIER PROGRAMMING OF NAND FLASH MEMORY Mar 16, 2011 Abandoned
Array ( [id] => 7697987 [patent_doc_number] => 20110228603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'FUSION MEMORY' [patent_app_type] => utility [patent_app_number] => 13/049504 [patent_app_country] => US [patent_app_date] => 2011-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 15032 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20110228603.pdf [firstpage_image] =>[orig_patent_app_number] => 13049504 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/049504
Fusion memory Mar 15, 2011 Issued
Array ( [id] => 6013215 [patent_doc_number] => 20110222348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Nonvolatile Memory Devices Having Memory Cell Arrays with Unequal-Sized Memory Cells and Methods of Operating Same' [patent_app_type] => utility [patent_app_number] => 13/035369 [patent_app_country] => US [patent_app_date] => 2011-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7200 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20110222348.pdf [firstpage_image] =>[orig_patent_app_number] => 13035369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/035369
Nonvolatile memory devices having memory cell arrays with unequal-sized memory cells and methods of operating same Feb 24, 2011 Issued
Array ( [id] => 6210797 [patent_doc_number] => 20110134681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/027798 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7955 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20110134681.pdf [firstpage_image] =>[orig_patent_app_number] => 13027798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/027798
Semiconductor memory device Feb 14, 2011 Issued
Array ( [id] => 8521258 [patent_doc_number] => 20120320666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'Magnetoresistive Element and Magnetic Memory' [patent_app_type] => utility [patent_app_number] => 13/578866 [patent_app_country] => US [patent_app_date] => 2011-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6203 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13578866 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/578866
Magnetoresistive element and magnetic memory Feb 13, 2011 Issued
Array ( [id] => 8785870 [patent_doc_number] => 08432721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Method of programming variable resistance element, method of initializing variable resistance element, and nonvolatile storage device' [patent_app_type] => utility [patent_app_number] => 13/201890 [patent_app_country] => US [patent_app_date] => 2011-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 18945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13201890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/201890
Method of programming variable resistance element, method of initializing variable resistance element, and nonvolatile storage device Jan 31, 2011 Issued
Array ( [id] => 6171149 [patent_doc_number] => 20110175654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'DATA OUTPUT CONTROL CIRCUIT AND DATA OUTPUT CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 13/017486 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8320 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175654.pdf [firstpage_image] =>[orig_patent_app_number] => 13017486 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/017486
Data output control circuit and data output control method Jan 30, 2011 Issued
Array ( [id] => 8761767 [patent_doc_number] => 08422297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Multi level inhibit scheme' [patent_app_type] => utility [patent_app_number] => 12/981688 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6153 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981688 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981688
Multi level inhibit scheme Dec 29, 2010 Issued
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