Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8534709 [patent_doc_number] => 08310868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Spin torque transfer memory cell structures and methods' [patent_app_type] => utility [patent_app_number] => 12/885054 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 10472 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12885054 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/885054
Spin torque transfer memory cell structures and methods Sep 16, 2010 Issued
Array ( [id] => 6157381 [patent_doc_number] => 20110157996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/884878 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11461 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20110157996.pdf [firstpage_image] =>[orig_patent_app_number] => 12884878 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/884878
Nonvolatile semiconductor memory device Sep 16, 2010 Issued
Array ( [id] => 4620424 [patent_doc_number] => 08000148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Methods of operating nonvolatile memory devices' [patent_app_type] => utility [patent_app_number] => 12/805501 [patent_app_country] => US [patent_app_date] => 2010-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5670 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/000/08000148.pdf [firstpage_image] =>[orig_patent_app_number] => 12805501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805501
Methods of operating nonvolatile memory devices Aug 2, 2010 Issued
Array ( [id] => 6147851 [patent_doc_number] => 20110019481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/843212 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12724 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20110019481.pdf [firstpage_image] =>[orig_patent_app_number] => 12843212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843212
Techniques for providing a direct injection semiconductor memory device Jul 25, 2010 Issued
Array ( [id] => 8898013 [patent_doc_number] => 08477540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Static memory device with five transistors and operating method' [patent_app_type] => utility [patent_app_number] => 12/842618 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8238 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12842618 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/842618
Static memory device with five transistors and operating method Jul 22, 2010 Issued
Array ( [id] => 8579257 [patent_doc_number] => 08345477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-01 [patent_title] => 'Non-volatile memory devices having uniform error distributions among pages' [patent_app_type] => utility [patent_app_number] => 12/842724 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12842724 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/842724
Non-volatile memory devices having uniform error distributions among pages Jul 22, 2010 Issued
Array ( [id] => 9525765 [patent_doc_number] => 08750049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Word line driver for memory' [patent_app_type] => utility [patent_app_number] => 12/840660 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6580 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12840660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840660
Word line driver for memory Jul 20, 2010 Issued
Array ( [id] => 7485219 [patent_doc_number] => 20110235456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'POWER SUPPLY CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/841086 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20110235456.pdf [firstpage_image] =>[orig_patent_app_number] => 12841086 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/841086
Power supply control circuit and semiconductor apparatus including the same Jul 20, 2010 Issued
Array ( [id] => 8726926 [patent_doc_number] => 08406061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/841014 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6154 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12841014 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/841014
Semiconductor memory apparatus Jul 20, 2010 Issued
Array ( [id] => 7571481 [patent_doc_number] => 20110267137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/840966 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8751 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20110267137.pdf [firstpage_image] =>[orig_patent_app_number] => 12840966 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840966
Semiconductor apparatus Jul 20, 2010 Issued
Array ( [id] => 8423177 [patent_doc_number] => 08279668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Apparatus and method of memory programming' [patent_app_type] => utility [patent_app_number] => 12/801532 [patent_app_country] => US [patent_app_date] => 2010-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8664 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12801532 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801532
Apparatus and method of memory programming Jun 13, 2010 Issued
Array ( [id] => 6259283 [patent_doc_number] => 20100296350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'METHOD OF SETTING READ VOLTAGE MINIMIZING READ DATA ERRORS' [patent_app_type] => utility [patent_app_number] => 12/774814 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6379 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20100296350.pdf [firstpage_image] =>[orig_patent_app_number] => 12774814 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774814
Method of setting read voltage minimizing read data errors May 5, 2010 Issued
Array ( [id] => 6464544 [patent_doc_number] => 20100284216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'INFORMATION STORAGE DEVICES USING MAGNETIC DOMAIN WALL MOVEMENT AND METHODS OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/775160 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 20264 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20100284216.pdf [firstpage_image] =>[orig_patent_app_number] => 12775160 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775160
Information storage devices using magnetic domain wall movement and methods of operating the same May 5, 2010 Issued
Array ( [id] => 5966840 [patent_doc_number] => 20110149627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/774678 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2691 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20110149627.pdf [firstpage_image] =>[orig_patent_app_number] => 12774678 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774678
NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME May 4, 2010 Abandoned
Array ( [id] => 6532633 [patent_doc_number] => 20100287391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'MEMORY CONTROL CIRCUIT, CONTROL METHOD, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/774266 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287391.pdf [firstpage_image] =>[orig_patent_app_number] => 12774266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774266
Memory control circuit, control method, and storage medium May 4, 2010 Issued
Array ( [id] => 7560114 [patent_doc_number] => 20110273946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'UNIVERSAL TEST STRUCTURES BASED SRAM ON-CHIP PARAMETRIC TEST MODULE AND METHODS OF OPERATING AND TESTING' [patent_app_type] => utility [patent_app_number] => 12/774044 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20110273946.pdf [firstpage_image] =>[orig_patent_app_number] => 12774044 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774044
Universal test structures based SRAM on-chip parametric test module and methods of operating and testing May 4, 2010 Issued
Array ( [id] => 6053791 [patent_doc_number] => 20110110151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'MAGNETIC MEMORY WITH A THERMALLY ASSISTED SPIN TRANSFER TORQUE WRITING PROCEDURE USING A LOW WRITING CURRENT' [patent_app_type] => utility [patent_app_number] => 12/773318 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6474 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20110110151.pdf [firstpage_image] =>[orig_patent_app_number] => 12773318 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773318
Magnetic memory with a thermally assisted spin transfer torque writing procedure using a low writing current May 3, 2010 Issued
Array ( [id] => 6464527 [patent_doc_number] => 20100284215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'MAGNETIC MEMORY WITH A THERMALLY ASSISTED WRITING PROCEDURE AND REDUCED WRITING FIELD' [patent_app_type] => utility [patent_app_number] => 12/773072 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5841 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20100284215.pdf [firstpage_image] =>[orig_patent_app_number] => 12773072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773072
Magnetic memory with a thermally assisted writing procedure and reduced writing field May 3, 2010 Issued
Array ( [id] => 8666006 [patent_doc_number] => 08379474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Word line selection circuit and row decoder' [patent_app_type] => utility [patent_app_number] => 12/773404 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4973 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12773404 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773404
Word line selection circuit and row decoder May 3, 2010 Issued
Array ( [id] => 6286164 [patent_doc_number] => 20100157667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Capacitorless DRAM memory cell comprising a partially-depleted MOSFET device comprising a gate insulator in two parts' [patent_app_type] => utility [patent_app_number] => 12/659162 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3532 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20100157667.pdf [firstpage_image] =>[orig_patent_app_number] => 12659162 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659162
Capacitorless DRAM memory cell comprising a partially-depleted MOSFET device comprising a gate insulator in two parts Feb 25, 2010 Abandoned
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