Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6470071 [patent_doc_number] => 20100091549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Non-Volatile Memory Cell with Complementary Resistive Memory Elements' [patent_app_type] => utility [patent_app_number] => 12/501140 [patent_app_country] => US [patent_app_date] => 2009-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091549.pdf [firstpage_image] =>[orig_patent_app_number] => 12501140 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/501140
Non-volatile memory cell with complementary resistive memory elements Jul 9, 2009 Issued
Array ( [id] => 6474620 [patent_doc_number] => 20100008129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/501250 [patent_app_country] => US [patent_app_date] => 2009-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20100008129.pdf [firstpage_image] =>[orig_patent_app_number] => 12501250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/501250
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME Jul 9, 2009 Abandoned
Array ( [id] => 6564505 [patent_doc_number] => 20100128519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'NON VOLATILE MEMORY HAVING INCREASED SENSING MARGIN' [patent_app_type] => utility [patent_app_number] => 12/500172 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128519.pdf [firstpage_image] =>[orig_patent_app_number] => 12500172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500172
NON VOLATILE MEMORY HAVING INCREASED SENSING MARGIN Jul 8, 2009 Abandoned
Array ( [id] => 6577977 [patent_doc_number] => 20100061171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'Semiconductor Memory Device and Method of Operating the Same' [patent_app_type] => utility [patent_app_number] => 12/500242 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4463 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20100061171.pdf [firstpage_image] =>[orig_patent_app_number] => 12500242 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500242
Semiconductor memory device and method of operating the same Jul 8, 2009 Issued
Array ( [id] => 6133101 [patent_doc_number] => 20110007568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'NAND TYPE ROM' [patent_app_type] => utility [patent_app_number] => 12/500236 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1917 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20110007568.pdf [firstpage_image] =>[orig_patent_app_number] => 12500236 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500236
NAND TYPE ROM Jul 8, 2009 Abandoned
Array ( [id] => 6133143 [patent_doc_number] => 20110007587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'COMMAND LATENCY SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/500240 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6698 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20110007587.pdf [firstpage_image] =>[orig_patent_app_number] => 12500240 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500240
Command latency systems and methods Jul 8, 2009 Issued
Array ( [id] => 6530169 [patent_doc_number] => 20100124101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/499894 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3431 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124101.pdf [firstpage_image] =>[orig_patent_app_number] => 12499894 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499894
PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE Jul 8, 2009 Abandoned
Array ( [id] => 6133135 [patent_doc_number] => 20110007580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'LOCAL SENSING AND FEEDBACK FOR AN SRAM ARRAY' [patent_app_type] => utility [patent_app_number] => 12/499666 [patent_app_country] => US [patent_app_date] => 2009-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20110007580.pdf [firstpage_image] =>[orig_patent_app_number] => 12499666 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499666
Local sensing and feedback for an SRAM array Jul 7, 2009 Issued
Array ( [id] => 7980091 [patent_doc_number] => 08072798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/496844 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14730 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072798.pdf [firstpage_image] =>[orig_patent_app_number] => 12496844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496844
Semiconductor memory device Jul 1, 2009 Issued
Array ( [id] => 4459049 [patent_doc_number] => 07894296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations' [patent_app_type] => utility [patent_app_number] => 12/496976 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6767 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/894/07894296.pdf [firstpage_image] =>[orig_patent_app_number] => 12496976 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496976
Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations Jul 1, 2009 Issued
Array ( [id] => 6093188 [patent_doc_number] => 20110002152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'SYSTEMS, MEMORIES, AND METHODS FOR REPAIR IN OPEN DIGIT MEMORY ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 12/497192 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9065 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20110002152.pdf [firstpage_image] =>[orig_patent_app_number] => 12497192 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497192
Systems, memories, and methods for repair in open digit memory architectures Jul 1, 2009 Issued
Array ( [id] => 6368251 [patent_doc_number] => 20100080065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/496064 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 19092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080065.pdf [firstpage_image] =>[orig_patent_app_number] => 12496064 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496064
Nonvolatile semiconductor memory device and method for driving the same Jun 30, 2009 Issued
Array ( [id] => 6093267 [patent_doc_number] => 20110002186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'SECURE ELECTRICALLY PROGRAMMABLE FUSE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/496624 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20110002186.pdf [firstpage_image] =>[orig_patent_app_number] => 12496624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496624
SECURE ELECTRICALLY PROGRAMMABLE FUSE AND METHOD OF OPERATING THE SAME Jun 30, 2009 Abandoned
Array ( [id] => 7765521 [patent_doc_number] => 08116160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Methods of detecting a shift in the threshold voltage for a nonvolatile memory cell' [patent_app_type] => utility [patent_app_number] => 12/495546 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 4561 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/116/08116160.pdf [firstpage_image] =>[orig_patent_app_number] => 12495546 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495546
Methods of detecting a shift in the threshold voltage for a nonvolatile memory cell Jun 29, 2009 Issued
Array ( [id] => 8447717 [patent_doc_number] => 08289775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array' [patent_app_type] => utility [patent_app_number] => 12/456744 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 28768 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12456744 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/456744
Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array Jun 21, 2009 Issued
Array ( [id] => 8459412 [patent_doc_number] => 08295087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS' [patent_app_type] => utility [patent_app_number] => 12/456354 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 21371 [patent_no_of_claims] => 93 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12456354 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/456354
Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS Jun 15, 2009 Issued
Array ( [id] => 9525753 [patent_doc_number] => 08750037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 12/456440 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 5191 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12456440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/456440
Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof Jun 15, 2009 Issued
Array ( [id] => 6374769 [patent_doc_number] => 20100315869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'Spin torque transfer MRAM design with low switching current' [patent_app_type] => utility [patent_app_number] => 12/456324 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315869.pdf [firstpage_image] =>[orig_patent_app_number] => 12456324 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/456324
Spin torque transfer MRAM design with low switching current Jun 14, 2009 Abandoned
Array ( [id] => 4611894 [patent_doc_number] => 07995393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Flash memory device and system including the same' [patent_app_type] => utility [patent_app_number] => 12/457416 [patent_app_country] => US [patent_app_date] => 2009-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 9562 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/995/07995393.pdf [firstpage_image] =>[orig_patent_app_number] => 12457416 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457416
Flash memory device and system including the same Jun 9, 2009 Issued
Array ( [id] => 5372851 [patent_doc_number] => 20090310411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS' [patent_app_type] => utility [patent_app_number] => 12/455936 [patent_app_country] => US [patent_app_date] => 2009-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 23470 [patent_no_of_claims] => 101 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20090310411.pdf [firstpage_image] =>[orig_patent_app_number] => 12455936 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/455936
Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS Jun 8, 2009 Issued
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