Search

Sang H. Nguyen

Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2877, 2886
Total Applications
2464
Issued Applications
2109
Pending Applications
129
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5471841 [patent_doc_number] => 20090245007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'SELECTIVELY CONTROLLED MEMORY' [patent_app_type] => utility [patent_app_number] => 12/059640 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20090245007.pdf [firstpage_image] =>[orig_patent_app_number] => 12059640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/059640
Selectively controlled memory Mar 30, 2008 Issued
Array ( [id] => 5329284 [patent_doc_number] => 20090109761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Method of operating nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 12/076310 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109761.pdf [firstpage_image] =>[orig_patent_app_number] => 12076310 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076310
Method of operating nonvolatile memory device Mar 16, 2008 Abandoned
Array ( [id] => 4445185 [patent_doc_number] => 07929363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-19 [patent_title] => 'Memory test and setup method' [patent_app_type] => utility [patent_app_number] => 12/075552 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1736 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/929/07929363.pdf [firstpage_image] =>[orig_patent_app_number] => 12075552 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/075552
Memory test and setup method Mar 11, 2008 Issued
Array ( [id] => 4790752 [patent_doc_number] => 20080291725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Memory cell array and semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/073968 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5362 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20080291725.pdf [firstpage_image] =>[orig_patent_app_number] => 12073968 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073968
Memory cell array and semiconductor memory Mar 11, 2008 Issued
Array ( [id] => 5519990 [patent_doc_number] => 20090027971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Apparatuses, computer program products and methods for reading data from memory cells' [patent_app_type] => utility [patent_app_number] => 12/073842 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4055 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027971.pdf [firstpage_image] =>[orig_patent_app_number] => 12073842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073842
Apparatuses, computer program products and methods for reading data from memory cells Mar 10, 2008 Issued
Array ( [id] => 4818339 [patent_doc_number] => 20080225598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Flash memory and method for checking status register by block unit' [patent_app_type] => utility [patent_app_number] => 12/075398 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3572 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20080225598.pdf [firstpage_image] =>[orig_patent_app_number] => 12075398 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/075398
Flash memory and method for checking status register by block unit Mar 10, 2008 Abandoned
Array ( [id] => 5308826 [patent_doc_number] => 20090016107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Methods of operating nonvolatile memory devices' [patent_app_type] => utility [patent_app_number] => 12/073314 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5639 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016107.pdf [firstpage_image] =>[orig_patent_app_number] => 12073314 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073314
Methods of operating nonvolatile memory devices Mar 3, 2008 Issued
Array ( [id] => 5584171 [patent_doc_number] => 20090103373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS' [patent_app_type] => utility [patent_app_number] => 12/039680 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9421 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20090103373.pdf [firstpage_image] =>[orig_patent_app_number] => 12039680 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039680
HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS Feb 27, 2008 Abandoned
Array ( [id] => 186834 [patent_doc_number] => 07649797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Self-refresh control circuit and semiconductor memory device including the same' [patent_app_type] => utility [patent_app_number] => 12/031110 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649797.pdf [firstpage_image] =>[orig_patent_app_number] => 12031110 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031110
Self-refresh control circuit and semiconductor memory device including the same Feb 13, 2008 Issued
Array ( [id] => 5329295 [patent_doc_number] => 20090109772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'RAM WITH INDEPENDENT LOCAL CLOCK' [patent_app_type] => utility [patent_app_number] => 12/031504 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10356 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109772.pdf [firstpage_image] =>[orig_patent_app_number] => 12031504 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031504
RAM WITH INDEPENDENT LOCAL CLOCK Feb 13, 2008 Abandoned
Array ( [id] => 5574193 [patent_doc_number] => 20090141554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'MEMORY DEVICE HAVING SMALL ARRAY AREA' [patent_app_type] => utility [patent_app_number] => 12/030472 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20090141554.pdf [firstpage_image] =>[orig_patent_app_number] => 12030472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030472
MEMORY DEVICE HAVING SMALL ARRAY AREA Feb 12, 2008 Abandoned
Array ( [id] => 4865352 [patent_doc_number] => 20080144411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Memory Module Including A Plurality Of Integrated Circuit Memory Devices And A Plurality Of Buffer Devices In A Matrix Topology' [patent_app_type] => utility [patent_app_number] => 12/030332 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12101 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144411.pdf [firstpage_image] =>[orig_patent_app_number] => 12030332 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030332
Memory Module Including A Plurality Of Integrated Circuit Memory Devices And A Plurality Of Buffer Devices In A Matrix Topology Feb 12, 2008 Abandoned
Array ( [id] => 44949 [patent_doc_number] => 07782645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-24 [patent_title] => 'Selective encoding of data values for memory cell blocks' [patent_app_type] => utility [patent_app_number] => 12/012660 [patent_app_country] => US [patent_app_date] => 2008-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 7657 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782645.pdf [firstpage_image] =>[orig_patent_app_number] => 12012660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/012660
Selective encoding of data values for memory cell blocks Feb 3, 2008 Issued
Array ( [id] => 4953741 [patent_doc_number] => 20080186765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/020628 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20080186765.pdf [firstpage_image] =>[orig_patent_app_number] => 12020628 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/020628
SEMICONDUCTOR MEMORY DEVICE Jan 27, 2008 Abandoned
Array ( [id] => 5584170 [patent_doc_number] => 20090103372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS' [patent_app_type] => utility [patent_app_number] => 11/933556 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9005 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20090103372.pdf [firstpage_image] =>[orig_patent_app_number] => 11933556 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933556
HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS Oct 31, 2007 Abandoned
Array ( [id] => 5584185 [patent_doc_number] => 20090103387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS' [patent_app_type] => utility [patent_app_number] => 11/874914 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6480 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20090103387.pdf [firstpage_image] =>[orig_patent_app_number] => 11874914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/874914
HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS Oct 18, 2007 Abandoned
Array ( [id] => 5334954 [patent_doc_number] => 20090051418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'DISTRIBUTED VOLTAGE REGULATOR' [patent_app_type] => utility [patent_app_number] => 11/842254 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5570 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20090051418.pdf [firstpage_image] =>[orig_patent_app_number] => 11842254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842254
DISTRIBUTED VOLTAGE REGULATOR Aug 20, 2007 Abandoned
Array ( [id] => 327697 [patent_doc_number] => 07515478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'CMOS logic compatible non-volatile memory cell structure, operation, and array configuration' [patent_app_type] => utility [patent_app_number] => 11/841468 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4758 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/515/07515478.pdf [firstpage_image] =>[orig_patent_app_number] => 11841468 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/841468
CMOS logic compatible non-volatile memory cell structure, operation, and array configuration Aug 19, 2007 Issued
Array ( [id] => 4668500 [patent_doc_number] => 20080043560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'DUAL MODE SRAM ARCHITECTURE FOR VOLTAGE SCALING AND POWER MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 11/841310 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20080043560.pdf [firstpage_image] =>[orig_patent_app_number] => 11841310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/841310
Dual mode SRAM architecture for voltage scaling and power management Aug 19, 2007 Issued
Array ( [id] => 257345 [patent_doc_number] => 07577025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Semiconductor memory device comprising floating body memory cells and related methods of operation' [patent_app_type] => utility [patent_app_number] => 11/841058 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9085 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577025.pdf [firstpage_image] =>[orig_patent_app_number] => 11841058 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/841058
Semiconductor memory device comprising floating body memory cells and related methods of operation Aug 19, 2007 Issued
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