Sang H. Nguyen

Array ( [id] => 74027 [patent_doc_number] => 07755951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Data output apparatus, memory system, data output method, and data processing method' [patent_app_type] => utility [patent_app_number] => 11/840912 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 5696 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/755/07755951.pdf [firstpage_image] =>[orig_patent_app_number] => 11840912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5445306 [patent_doc_number] => 20090046532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Supply Voltage for Memory Device' [patent_app_type] => utility [patent_app_number] => 11/840314 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5762 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20090046532.pdf [firstpage_image] =>[orig_patent_app_number] => 11840314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 293396 [patent_doc_number] => 07545694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Sense amplifier with leakage testing and read debug capability' [patent_app_type] => utility [patent_app_number] => 11/839632 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4313 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/545/07545694.pdf [firstpage_image] =>[orig_patent_app_number] => 11839632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5445276 [patent_doc_number] => 20090046502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Metal Magnetic Memory Cell' [patent_app_type] => utility [patent_app_number] => 11/839710 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1881 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20090046502.pdf [firstpage_image] =>[orig_patent_app_number] => 11839710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16064 [patent_doc_number] => 07808843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Integrated circuit and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/839262 [patent_app_country] => US [patent_app_date] => 2007-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3803 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808843.pdf [firstpage_image] =>[orig_patent_app_number] => 11839262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7594585 [patent_doc_number] => 07626878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-01 [patent_title] => 'Active bit line charge keeper' [patent_app_type] => utility [patent_app_number] => 11/838818 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626878.pdf [firstpage_image] =>[orig_patent_app_number] => 11838818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4732529 [patent_doc_number] => 20080049508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY, ITS READ METHOD AND A MEMORY CARD' [patent_app_type] => utility [patent_app_number] => 11/838510 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049508.pdf [firstpage_image] =>[orig_patent_app_number] => 11838510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4668493 [patent_doc_number] => 20080043553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/837722 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6397 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20080043553.pdf [firstpage_image] =>[orig_patent_app_number] => 11837722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 279034 [patent_doc_number] => 07558116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Regulation of boost-strap node ramp rate using capacitance to counter parasitic elements in channel' [patent_app_type] => utility [patent_app_number] => 11/837976 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558116.pdf [firstpage_image] =>[orig_patent_app_number] => 11837976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4650076 [patent_doc_number] => 20080037332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE AND ELECTRONIC EQUIPMENT' [patent_app_type] => utility [patent_app_number] => 11/836632 [patent_app_country] => US [patent_app_date] => 2007-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8155 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20080037332.pdf [firstpage_image] =>[orig_patent_app_number] => 11836632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8109721 [patent_doc_number] => 08156515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Optical recording medium and reproducing device' [patent_app_type] => utility [patent_app_number] => 12/375648 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14415 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156515.pdf [firstpage_image] =>[orig_patent_app_number] => 12375648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 346165 [patent_doc_number] => 07499357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/819787 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2208 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499357.pdf [firstpage_image] =>[orig_patent_app_number] => 11819787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4709605 [patent_doc_number] => 20080298131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'INTEGRATED CIRCUIT FEATURING A NON-VOLATILE MEMORY WITH CHARGE/DISCHARGE RAMP RATE CONTROL AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/756192 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20080298131.pdf [firstpage_image] =>[orig_patent_app_number] => 11756192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 124293 [patent_doc_number] => 07710801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Circuitry and method for an at-speed scan test' [patent_app_type] => utility [patent_app_number] => 11/755758 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7525 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/710/07710801.pdf [firstpage_image] =>[orig_patent_app_number] => 11755758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4625614 [patent_doc_number] => 08004920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Power saving memory apparatus, systems, and methods' [patent_app_type] => utility [patent_app_number] => 11/754756 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10372 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004920.pdf [firstpage_image] =>[orig_patent_app_number] => 11754756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4844580 [patent_doc_number] => 20080180988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'DIRECT WRITING METHOD OF MAGNETIC MEMORY CELL AND MAGETIC MEMORY CELL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/754308 [patent_app_country] => US [patent_app_date] => 2007-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4146 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20080180988.pdf [firstpage_image] =>[orig_patent_app_number] => 11754308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 178992 [patent_doc_number] => 07656703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Method for using transitional voltage during programming of non-volatile storage' [patent_app_type] => utility [patent_app_number] => 11/753958 [patent_app_country] => US [patent_app_date] => 2007-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 12465 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/656/07656703.pdf [firstpage_image] =>[orig_patent_app_number] => 11753958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5009502 [patent_doc_number] => 20070279980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'READING METHOD OF A NON-VOLATILE ELECTRONIC DEVICE AND CORRESPONDING DEVICE' [patent_app_type] => utility [patent_app_number] => 11/753368 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3837 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20070279980.pdf [firstpage_image] =>[orig_patent_app_number] => 11753368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 335309 [patent_doc_number] => 07508723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Buffered memory device' [patent_app_type] => utility [patent_app_number] => 11/753460 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4415 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/508/07508723.pdf [firstpage_image] =>[orig_patent_app_number] => 11753460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4790787 [patent_doc_number] => 20080291760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Sub-array architecture memory devices and related systems and methods' [patent_app_type] => utility [patent_app_number] => 11/805750 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5346 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20080291760.pdf [firstpage_image] =>[orig_patent_app_number] => 11805750 [rel_patent_id] =>[rel_patent_doc_number] =>)