
Sang H. Nguyen
Examiner (ID: 14839, Phone: (571)272-2425 , Office: P/2886 )
| Most Active Art Unit | 2877 |
| Art Unit(s) | 2877, 2886 |
| Total Applications | 2464 |
| Issued Applications | 2109 |
| Pending Applications | 129 |
| Abandoned Applications | 259 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 572039
[patent_doc_number] => 07471537
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-12-30
[patent_title] => 'Content addressable memories (CAM) having low power dynamic match line sensing circuits therein'
[patent_app_type] => utility
[patent_app_number] => 11/751900
[patent_app_country] => US
[patent_app_date] => 2007-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 3427
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/471/07471537.pdf
[firstpage_image] =>[orig_patent_app_number] => 11751900
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/751900 | Content addressable memories (CAM) having low power dynamic match line sensing circuits therein | May 21, 2007 | Issued |
Array
(
[id] => 5082923
[patent_doc_number] => 20070272974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-29
[patent_title] => 'TWIN-GATE NON-VOLATILE MEMORY CELL AND METHOD OF OPERATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/752250
[patent_app_country] => US
[patent_app_date] => 2007-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7135
[patent_no_of_claims] => 25
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[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0272/20070272974.pdf
[firstpage_image] =>[orig_patent_app_number] => 11752250
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/752250 | TWIN-GATE NON-VOLATILE MEMORY CELL AND METHOD OF OPERATING THE SAME | May 21, 2007 | Abandoned |
Array
(
[id] => 218153
[patent_doc_number] => 07613060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-03
[patent_title] => 'Methods, circuits, and systems to select memory regions'
[patent_app_type] => utility
[patent_app_number] => 11/805092
[patent_app_country] => US
[patent_app_date] => 2007-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4985
[patent_no_of_claims] => 13
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/613/07613060.pdf
[firstpage_image] =>[orig_patent_app_number] => 11805092
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/805092 | Methods, circuits, and systems to select memory regions | May 20, 2007 | Issued |
Array
(
[id] => 4686873
[patent_doc_number] => 20080031054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-07
[patent_title] => 'Read-out circuit for or in a Rom memory; Rom memory and method for reading the Rom memory'
[patent_app_type] => utility
[patent_app_number] => 11/803852
[patent_app_country] => US
[patent_app_date] => 2007-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8759
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20080031054.pdf
[firstpage_image] =>[orig_patent_app_number] => 11803852
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/803852 | Read-out circuit for or in a ROM memory; ROM memory and method for reading the ROM memory | May 15, 2007 | Issued |
Array
(
[id] => 4777356
[patent_doc_number] => 20080285354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-20
[patent_title] => 'Self reference sensing system and method'
[patent_app_type] => utility
[patent_app_number] => 11/804170
[patent_app_country] => US
[patent_app_date] => 2007-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4584
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20080285354.pdf
[firstpage_image] =>[orig_patent_app_number] => 11804170
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/804170 | Self reference sensing system and method | May 15, 2007 | Abandoned |
Array
(
[id] => 4686874
[patent_doc_number] => 20080031055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-07
[patent_title] => 'Semiconductor memory device capable of performing low-frequency test operation and method for testing the same'
[patent_app_type] => utility
[patent_app_number] => 11/803454
[patent_app_country] => US
[patent_app_date] => 2007-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 5077
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20080031055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11803454
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/803454 | Semiconductor memory device capable of performing low-frequency test operation and method for testing the same | May 14, 2007 | Issued |
Array
(
[id] => 4858144
[patent_doc_number] => 20080266994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'LEVEL DETECT CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/741192
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5278
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20080266994.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741192
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741192 | Level detect circuit | Apr 26, 2007 | Issued |
Array
(
[id] => 564485
[patent_doc_number] => 07468916
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-23
[patent_title] => 'Non-volatile memory having a row driving circuit with shared level shift circuits'
[patent_app_type] => utility
[patent_app_number] => 11/688262
[patent_app_country] => US
[patent_app_date] => 2007-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3855
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 688
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/468/07468916.pdf
[firstpage_image] =>[orig_patent_app_number] => 11688262
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/688262 | Non-volatile memory having a row driving circuit with shared level shift circuits | Mar 19, 2007 | Issued |
Array
(
[id] => 4738517
[patent_doc_number] => 20080232169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES'
[patent_app_type] => utility
[patent_app_number] => 11/688740
[patent_app_country] => US
[patent_app_date] => 2007-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2414
[patent_no_of_claims] => 18
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[pdf_file] => publications/A1/0232/20080232169.pdf
[firstpage_image] =>[orig_patent_app_number] => 11688740
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/688740 | NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES | Mar 19, 2007 | Abandoned |
Array
(
[id] => 4741888
[patent_doc_number] => 20080235541
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'METHOD FOR TESTING A WORD LINE FAILURE'
[patent_app_type] => utility
[patent_app_number] => 11/688240
[patent_app_country] => US
[patent_app_date] => 2007-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3688
[patent_no_of_claims] => 16
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20080235541.pdf
[firstpage_image] =>[orig_patent_app_number] => 11688240
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/688240 | METHOD FOR TESTING A WORD LINE FAILURE | Mar 18, 2007 | Abandoned |
Array
(
[id] => 4976045
[patent_doc_number] => 20070217276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'FUSE LATCH CIRCUIT, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 11/687084
[patent_app_country] => US
[patent_app_date] => 2007-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0217/20070217276.pdf
[firstpage_image] =>[orig_patent_app_number] => 11687084
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/687084 | FUSE LATCH CIRCUIT, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY SYSTEM | Mar 15, 2007 | Abandoned |
Array
(
[id] => 4818348
[patent_doc_number] => 20080225607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-18
[patent_title] => 'DIVISION-BASED SENSING AND PARTITIONING OF ELECTRONIC MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/687436
[patent_app_country] => US
[patent_app_date] => 2007-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => publications/A1/0225/20080225607.pdf
[firstpage_image] =>[orig_patent_app_number] => 11687436
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/687436 | Division-based sensing and partitioning of electronic memory | Mar 15, 2007 | Issued |
Array
(
[id] => 4587594
[patent_doc_number] => 07835189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-16
[patent_title] => 'High accuracy adaptive programming'
[patent_app_type] => utility
[patent_app_number] => 11/687492
[patent_app_country] => US
[patent_app_date] => 2007-03-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/835/07835189.pdf
[firstpage_image] =>[orig_patent_app_number] => 11687492
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/687492 | High accuracy adaptive programming | Mar 15, 2007 | Issued |
Array
(
[id] => 4942939
[patent_doc_number] => 20080080264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'Internal voltage generator'
[patent_app_type] => utility
[patent_app_number] => 11/716633
[patent_app_country] => US
[patent_app_date] => 2007-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0080/20080080264.pdf
[firstpage_image] =>[orig_patent_app_number] => 11716633
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/716633 | Internal voltage generator | Mar 11, 2007 | Issued |
Array
(
[id] => 4942942
[patent_doc_number] => 20080080267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'DATA OUTPUT CONTROL CIRCUIT AND DATA OUTPUT CONTROL METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/683490
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[pdf_file] => publications/A1/0080/20080080267.pdf
[firstpage_image] =>[orig_patent_app_number] => 11683490
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/683490 | DATA OUTPUT CONTROL CIRCUIT AND DATA OUTPUT CONTROL METHOD | Mar 7, 2007 | Abandoned |
Array
(
[id] => 5229469
[patent_doc_number] => 20070291576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'ADDRESS LATCH CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/683532
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[patent_app_date] => 2007-03-08
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[pdf_file] => publications/A1/0291/20070291576.pdf
[firstpage_image] =>[orig_patent_app_number] => 11683532
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/683532 | Address latch circuit of semiconductor memory device | Mar 7, 2007 | Issued |
Array
(
[id] => 4696875
[patent_doc_number] => 20080219059
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[patent_issue_date] => 2008-09-11
[patent_title] => 'Method for Cache Page Copy in a Non-Volatile Memory'
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[patent_app_number] => 11/683356
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/683356 | Method for cache page copy in a non-volatile memory | Mar 6, 2007 | Issued |
Array
(
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Array
(
[id] => 5015074
[patent_doc_number] => 20070258282
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[patent_title] => 'MAGNETIC MEMORY DEVICE AND METHOD OF WRITING DATA IN THE SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/682934 | MAGNETIC MEMORY DEVICE AND METHOD OF WRITING DATA IN THE SAME | Mar 6, 2007 | Abandoned |
Array
(
[id] => 5130022
[patent_doc_number] => 20070206419
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[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11682564
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/682564 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE | Mar 5, 2007 | Abandoned |