Search

Sara Elizabeth Townsley

Examiner (ID: 2446, Phone: (571)270-7672 , Office: P/1629 )

Most Active Art Unit
1629
Art Unit(s)
1629, 1612, 1613
Total Applications
514
Issued Applications
97
Pending Applications
81
Abandoned Applications
352

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2880505 [patent_doc_number] => 05153881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-06 [patent_title] => 'Method of handling errors in software' [patent_app_type] => 1 [patent_app_number] => 7/388041 [patent_app_country] => US [patent_app_date] => 1989-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 45 [patent_no_of_words] => 28836 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/153/05153881.pdf [firstpage_image] =>[orig_patent_app_number] => 388041 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/388041
Method of handling errors in software Jul 31, 1989 Issued
Array ( [id] => 2859222 [patent_doc_number] => 05111458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Hardware arrangement for storing error information in pipelined data processing system and method therefor' [patent_app_type] => 1 [patent_app_number] => 7/385192 [patent_app_country] => US [patent_app_date] => 1989-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2578 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111458.pdf [firstpage_image] =>[orig_patent_app_number] => 385192 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/385192
Hardware arrangement for storing error information in pipelined data processing system and method therefor Jul 25, 1989 Issued
Array ( [id] => 2557428 [patent_doc_number] => RE033462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-27 [patent_title] => 'Method and apparatus for transmitting digital data' [patent_app_type] => 2 [patent_app_number] => 7/379627 [patent_app_country] => US [patent_app_date] => 1989-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8031 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/033/RE033462.pdf [firstpage_image] =>[orig_patent_app_number] => 379627 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/379627
Method and apparatus for transmitting digital data Jul 12, 1989 Issued
Array ( [id] => 2754118 [patent_doc_number] => 05029169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Methods and apparatus for fault detection' [patent_app_type] => 1 [patent_app_number] => 7/378162 [patent_app_country] => US [patent_app_date] => 1989-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4306 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/029/05029169.pdf [firstpage_image] =>[orig_patent_app_number] => 378162 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/378162
Methods and apparatus for fault detection Jul 10, 1989 Issued
Array ( [id] => 2680562 [patent_doc_number] => 05048018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'Debugging parallel programs by serialization' [patent_app_type] => 1 [patent_app_number] => 7/373953 [patent_app_country] => US [patent_app_date] => 1989-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 5713 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/048/05048018.pdf [firstpage_image] =>[orig_patent_app_number] => 373953 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/373953
Debugging parallel programs by serialization Jun 28, 1989 Issued
Array ( [id] => 2832482 [patent_doc_number] => 05095485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Microprocessor equipped with parity control unit on same chip' [patent_app_type] => 1 [patent_app_number] => 7/371222 [patent_app_country] => US [patent_app_date] => 1989-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4069 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/095/05095485.pdf [firstpage_image] =>[orig_patent_app_number] => 371222 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/371222
Microprocessor equipped with parity control unit on same chip Jun 25, 1989 Issued
07/370441 FAULT-TOLERANT SYSTEM AND METHOD FOR IMPLEMENTING A DISTRIBUTED STATE MACHINE Jun 22, 1989 Abandoned
Array ( [id] => 2892761 [patent_doc_number] => 05109506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Microcomputer system including a microprocessor reset circuit' [patent_app_type] => 1 [patent_app_number] => 7/367653 [patent_app_country] => US [patent_app_date] => 1989-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5337 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109506.pdf [firstpage_image] =>[orig_patent_app_number] => 367653 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/367653
Microcomputer system including a microprocessor reset circuit Jun 18, 1989 Issued
Array ( [id] => 2680580 [patent_doc_number] => 05048019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'Method of testing a read-only memory and device for performing the method' [patent_app_type] => 1 [patent_app_number] => 7/366571 [patent_app_country] => US [patent_app_date] => 1989-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2992 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/048/05048019.pdf [firstpage_image] =>[orig_patent_app_number] => 366571 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/366571
Method of testing a read-only memory and device for performing the method Jun 14, 1989 Issued
Array ( [id] => 2742838 [patent_doc_number] => 05033049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-16 [patent_title] => 'On-board diagnostic sub-system for SCSI interface' [patent_app_type] => 1 [patent_app_number] => 7/364363 [patent_app_country] => US [patent_app_date] => 1989-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3299 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/033/05033049.pdf [firstpage_image] =>[orig_patent_app_number] => 364363 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/364363
On-board diagnostic sub-system for SCSI interface Jun 11, 1989 Issued
Array ( [id] => 2744813 [patent_doc_number] => 05052000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Technique for improving the operation of decision feedback equalizers in communications systems utilizing error correction' [patent_app_type] => 1 [patent_app_number] => 7/363793 [patent_app_country] => US [patent_app_date] => 1989-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4129 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/052/05052000.pdf [firstpage_image] =>[orig_patent_app_number] => 363793 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/363793
Technique for improving the operation of decision feedback equalizers in communications systems utilizing error correction Jun 8, 1989 Issued
Array ( [id] => 2665567 [patent_doc_number] => 04972415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-20 [patent_title] => 'Voter subsystem for a fault tolerant multiple node processing system' [patent_app_type] => 1 [patent_app_number] => 7/362960 [patent_app_country] => US [patent_app_date] => 1989-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 98 [patent_no_of_words] => 54155 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/972/04972415.pdf [firstpage_image] =>[orig_patent_app_number] => 362960 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/362960
Voter subsystem for a fault tolerant multiple node processing system Jun 6, 1989 Issued
Array ( [id] => 2776870 [patent_doc_number] => 05036515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-30 [patent_title] => 'Bit error rate detection' [patent_app_type] => 1 [patent_app_number] => 7/358773 [patent_app_country] => US [patent_app_date] => 1989-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/036/05036515.pdf [firstpage_image] =>[orig_patent_app_number] => 358773 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/358773
Bit error rate detection May 29, 1989 Issued
Array ( [id] => 2603228 [patent_doc_number] => 04918691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-17 [patent_title] => 'Testing of integrated circuit modules' [patent_app_type] => 1 [patent_app_number] => 7/358291 [patent_app_country] => US [patent_app_date] => 1989-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3645 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/918/04918691.pdf [firstpage_image] =>[orig_patent_app_number] => 358291 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/358291
Testing of integrated circuit modules May 29, 1989 Issued
07/357453 APPARATUS AND METHOD FOR PROVIDING NOTIFICATION OF BIT-CELL FAILURE IN A REDUNDANT-BIT-CELL MEMORY May 25, 1989 Abandoned
Array ( [id] => 2754156 [patent_doc_number] => 05029171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Test vector generation system' [patent_app_type] => 1 [patent_app_number] => 7/356493 [patent_app_country] => US [patent_app_date] => 1989-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/029/05029171.pdf [firstpage_image] =>[orig_patent_app_number] => 356493 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/356493
Test vector generation system May 24, 1989 Issued
Array ( [id] => 2859289 [patent_doc_number] => 05111462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Decoders for Hamming encoded data' [patent_app_type] => 1 [patent_app_number] => 7/356041 [patent_app_country] => US [patent_app_date] => 1989-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3155 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111462.pdf [firstpage_image] =>[orig_patent_app_number] => 356041 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/356041
Decoders for Hamming encoded data May 22, 1989 Issued
07/354343 PASSIVE NETWORK MONITOR May 18, 1989 Abandoned
Array ( [id] => 2783810 [patent_doc_number] => 05075892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-24 [patent_title] => 'Parallel read circuit for testing high density memories' [patent_app_type] => 1 [patent_app_number] => 7/354244 [patent_app_country] => US [patent_app_date] => 1989-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3196 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/075/05075892.pdf [firstpage_image] =>[orig_patent_app_number] => 354244 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/354244
Parallel read circuit for testing high density memories May 18, 1989 Issued
Array ( [id] => 2604794 [patent_doc_number] => 04933940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-12 [patent_title] => 'Operations controller for a fault tolerant multiple node processing system' [patent_app_type] => 1 [patent_app_number] => 7/351876 [patent_app_country] => US [patent_app_date] => 1989-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 96 [patent_no_of_words] => 54107 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/933/04933940.pdf [firstpage_image] =>[orig_patent_app_number] => 351876 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/351876
Operations controller for a fault tolerant multiple node processing system May 11, 1989 Issued
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