Sara Elizabeth Townsley

Array ( [id] => 2645230 [patent_doc_number] => 04899340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-06 [patent_title] => 'Error correcting code and error correcting circuit using the same' [patent_app_type] => 1 [patent_app_number] => 7/212601 [patent_app_country] => US [patent_app_date] => 1988-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 15875 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/899/04899340.pdf [firstpage_image] =>[orig_patent_app_number] => 212601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2638486 [patent_doc_number] => 04907229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-06 [patent_title] => 'Selective multimode/multiconfigurable data acquisition and reduction processor system' [patent_app_type] => 1 [patent_app_number] => 7/211522 [patent_app_country] => US [patent_app_date] => 1988-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 44589 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/907/04907229.pdf [firstpage_image] =>[orig_patent_app_number] => 211522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2640132 [patent_doc_number] => 04916702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-10 [patent_title] => 'Elongated burst trapping' [patent_app_type] => 1 [patent_app_number] => 7/207811 [patent_app_country] => US [patent_app_date] => 1988-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7048 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/916/04916702.pdf [firstpage_image] =>[orig_patent_app_number] => 207811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2596344 [patent_doc_number] => 04926425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-15 [patent_title] => 'System for testing digital circuits' [patent_app_type] => 1 [patent_app_number] => 7/204622 [patent_app_country] => US [patent_app_date] => 1988-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2306 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/926/04926425.pdf [firstpage_image] =>[orig_patent_app_number] => 204622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2602530 [patent_doc_number] => 04941144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-10 [patent_title] => 'Data transmission device capable of adaptively varying a packet size without an increase in hardware' [patent_app_type] => 1 [patent_app_number] => 7/202291 [patent_app_country] => US [patent_app_date] => 1988-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3935 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/941/04941144.pdf [firstpage_image] =>[orig_patent_app_number] => 202291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2655746 [patent_doc_number] => 04896323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-23 [patent_title] => 'Parity-checked clock generator system' [patent_app_type] => 1 [patent_app_number] => 7/202283 [patent_app_country] => US [patent_app_date] => 1988-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1698 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/896/04896323.pdf [firstpage_image] =>[orig_patent_app_number] => 202283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2572767 [patent_doc_number] => 04945537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-31 [patent_title] => 'Maximum length linearly occurring code sequence generator' [patent_app_type] => 1 [patent_app_number] => 7/202984 [patent_app_country] => US [patent_app_date] => 1988-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2863 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/945/04945537.pdf [firstpage_image] =>[orig_patent_app_number] => 202984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2603245 [patent_doc_number] => 04918692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-17 [patent_title] => 'Automated error detection for multiple block memory array chip and correction thereof' [patent_app_type] => 1 [patent_app_number] => 7/201413 [patent_app_country] => US [patent_app_date] => 1988-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6296 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/918/04918692.pdf [firstpage_image] =>[orig_patent_app_number] => 201413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2603281 [patent_doc_number] => 04918694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-17 [patent_title] => 'Method and apparatus for correction of errors in digital audio data' [patent_app_type] => 1 [patent_app_number] => 7/202192 [patent_app_country] => US [patent_app_date] => 1988-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2659 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/918/04918694.pdf [firstpage_image] =>[orig_patent_app_number] => 202192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2647977 [patent_doc_number] => 04914661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-03 [patent_title] => 'Method and apparatus for correcting errors in digital signals having phase fluctuations' [patent_app_type] => 1 [patent_app_number] => 7/198131 [patent_app_country] => US [patent_app_date] => 1988-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4222 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/914/04914661.pdf [firstpage_image] =>[orig_patent_app_number] => 198131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2608949 [patent_doc_number] => 04922492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-01 [patent_title] => 'Architecture and device for testable mixed analog and digital VLSI circuits' [patent_app_type] => 1 [patent_app_number] => 7/193623 [patent_app_country] => US [patent_app_date] => 1988-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2904 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/922/04922492.pdf [firstpage_image] =>[orig_patent_app_number] => 193623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2533319 [patent_doc_number] => 04873685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'Self-checking voting logic for fault tolerant computing applications' [patent_app_type] => 1 [patent_app_number] => 7/190311 [patent_app_country] => US [patent_app_date] => 1988-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3655 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873685.pdf [firstpage_image] =>[orig_patent_app_number] => 190311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2641048 [patent_doc_number] => 04937741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-26 [patent_title] => 'Synchronization of fault-tolerant parallel processing systems' [patent_app_type] => 1 [patent_app_number] => 7/187452 [patent_app_country] => US [patent_app_date] => 1988-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3855 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/937/04937741.pdf [firstpage_image] =>[orig_patent_app_number] => 187452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2619203 [patent_doc_number] => 04903264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-20 [patent_title] => 'Method and apparatus for handling out of order exceptions in a pipelined data unit' [patent_app_type] => 1 [patent_app_number] => 7/182551 [patent_app_country] => US [patent_app_date] => 1988-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3611 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/903/04903264.pdf [firstpage_image] =>[orig_patent_app_number] => 182551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2613485 [patent_doc_number] => 04912712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-27 [patent_title] => 'Fault detection circuit capable of detecting burst errors in an LRU memory' [patent_app_type] => 1 [patent_app_number] => 7/181582 [patent_app_country] => US [patent_app_date] => 1988-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1528 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/912/04912712.pdf [firstpage_image] =>[orig_patent_app_number] => 181582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2613745 [patent_doc_number] => 04949342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-14 [patent_title] => 'Code error detecting method' [patent_app_type] => 1 [patent_app_number] => 7/180063 [patent_app_country] => US [patent_app_date] => 1988-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6868 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/949/04949342.pdf [firstpage_image] =>[orig_patent_app_number] => 180063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2636978 [patent_doc_number] => 04967412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-30 [patent_title] => 'Serial data frame generator for testing telecommunications circuits' [patent_app_type] => 1 [patent_app_number] => 7/179373 [patent_app_country] => US [patent_app_date] => 1988-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4825 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/967/04967412.pdf [firstpage_image] =>[orig_patent_app_number] => 179373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2624528 [patent_doc_number] => 04943966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-24 [patent_title] => 'Memory diagnostic apparatus and method' [patent_app_type] => 1 [patent_app_number] => 7/179162 [patent_app_country] => US [patent_app_date] => 1988-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5210 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/943/04943966.pdf [firstpage_image] =>[orig_patent_app_number] => 179162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2520834 [patent_doc_number] => 04831624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-16 [patent_title] => 'Error detection method for sub-band coding' [patent_app_type] => 1 [patent_app_number] => 7/177300 [patent_app_country] => US [patent_app_date] => 1988-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7121 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/831/04831624.pdf [firstpage_image] =>[orig_patent_app_number] => 177300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2564286 [patent_doc_number] => 04897838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-30 [patent_title] => 'Semiconductor integrated circuit device subjected to scan-testing of internal logic function' [patent_app_type] => 1 [patent_app_number] => 7/175192 [patent_app_country] => US [patent_app_date] => 1988-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5056 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/897/04897838.pdf [firstpage_image] =>[orig_patent_app_number] => 175192 [rel_patent_id] =>[rel_patent_doc_number] =>)