Sara Elizabeth Townsley

Array ( [id] => 2566017 [patent_doc_number] => 04815077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-21 [patent_title] => 'Test system for electronic devices with radio frequency signature extraction means' [patent_app_type] => 1 [patent_app_number] => 7/008031 [patent_app_country] => US [patent_app_date] => 1987-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1951 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/815/04815077.pdf [firstpage_image] =>[orig_patent_app_number] => 008031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2390671 [patent_doc_number] => 04775978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-04 [patent_title] => 'Data error correction system' [patent_app_type] => 1 [patent_app_number] => 7/003961 [patent_app_country] => US [patent_app_date] => 1987-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8383 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/775/04775978.pdf [firstpage_image] =>[orig_patent_app_number] => 003961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2539389 [patent_doc_number] => 04862461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-29 [patent_title] => 'Packet switch network protocol' [patent_app_type] => 1 [patent_app_number] => 7/002351 [patent_app_country] => US [patent_app_date] => 1987-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8068 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/862/04862461.pdf [firstpage_image] =>[orig_patent_app_number] => 002351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2498758 [patent_doc_number] => 04802164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-31 [patent_title] => 'Method and apparatus for testing a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 7/000762 [patent_app_country] => US [patent_app_date] => 1987-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3975 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/802/04802164.pdf [firstpage_image] =>[orig_patent_app_number] => 000762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2390503 [patent_doc_number] => 04783785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-08 [patent_title] => 'Method and apparatus for diagnosis of logical circuits' [patent_app_type] => 1 [patent_app_number] => 7/000381 [patent_app_country] => US [patent_app_date] => 1987-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3087 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/783/04783785.pdf [firstpage_image] =>[orig_patent_app_number] => 000381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2510326 [patent_doc_number] => 04799155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-17 [patent_title] => 'Data processing system having a hierarchy of service computers including a state display' [patent_app_type] => 1 [patent_app_number] => 6/948111 [patent_app_country] => US [patent_app_date] => 1986-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 15178 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/799/04799155.pdf [firstpage_image] =>[orig_patent_app_number] => 948111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2568563 [patent_doc_number] => 04817094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-28 [patent_title] => 'Fault tolerant switch with selectable operating modes' [patent_app_type] => 1 [patent_app_number] => 6/948372 [patent_app_country] => US [patent_app_date] => 1986-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3019 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/817/04817094.pdf [firstpage_image] =>[orig_patent_app_number] => 948372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2398296 [patent_doc_number] => 04794597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-27 [patent_title] => 'Memory device equipped with a RAS circuit' [patent_app_type] => 1 [patent_app_number] => 6/945530 [patent_app_country] => US [patent_app_date] => 1986-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5158 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/794/04794597.pdf [firstpage_image] =>[orig_patent_app_number] => 945530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2525273 [patent_doc_number] => 04819232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-04 [patent_title] => 'Fault-tolerant multiprocessor arrangement' [patent_app_type] => 1 [patent_app_number] => 6/941991 [patent_app_country] => US [patent_app_date] => 1986-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 10185 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 751 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/819/04819232.pdf [firstpage_image] =>[orig_patent_app_number] => 941991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2556328 [patent_doc_number] => 04805173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-14 [patent_title] => 'Error control method and apparatus' [patent_app_type] => 1 [patent_app_number] => 6/939599 [patent_app_country] => US [patent_app_date] => 1986-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2272 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/805/04805173.pdf [firstpage_image] =>[orig_patent_app_number] => 939599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2402460 [patent_doc_number] => 04769818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-06 [patent_title] => 'Method and apparatus for coding digital data to permit correction of one or two incorrect data packets (bytes)' [patent_app_type] => 1 [patent_app_number] => 6/933758 [patent_app_country] => US [patent_app_date] => 1986-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 14431 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/769/04769818.pdf [firstpage_image] =>[orig_patent_app_number] => 933758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2498721 [patent_doc_number] => 04802162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-31 [patent_title] => 'Automatic protocol synthesizing system' [patent_app_type] => 1 [patent_app_number] => 6/930341 [patent_app_country] => US [patent_app_date] => 1986-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 33 [patent_no_of_words] => 7380 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/802/04802162.pdf [firstpage_image] =>[orig_patent_app_number] => 930341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2453835 [patent_doc_number] => 04750181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-07 [patent_title] => 'Dynamic circuit checking apparatus using data input and output comparisons for testing the data integrity of a circuit' [patent_app_type] => 1 [patent_app_number] => 6/927212 [patent_app_country] => US [patent_app_date] => 1986-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4247 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/750/04750181.pdf [firstpage_image] =>[orig_patent_app_number] => 927212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2451842 [patent_doc_number] => 04792954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-20 [patent_title] => 'Concurrent detection of errors in arithmetic data compression coding' [patent_app_type] => 1 [patent_app_number] => 6/925433 [patent_app_country] => US [patent_app_date] => 1986-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6795 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/792/04792954.pdf [firstpage_image] =>[orig_patent_app_number] => 925433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2453902 [patent_doc_number] => 04740968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-26 [patent_title] => 'ECC circuit failure detector/quick word verifier' [patent_app_type] => 1 [patent_app_number] => 6/923522 [patent_app_country] => US [patent_app_date] => 1986-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5579 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/740/04740968.pdf [firstpage_image] =>[orig_patent_app_number] => 923522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2453619 [patent_doc_number] => 04745604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-17 [patent_title] => 'Method and apparatus for transferring data between a host processor and a data storage device' [patent_app_type] => 1 [patent_app_number] => 6/921022 [patent_app_country] => US [patent_app_date] => 1986-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3472 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/745/04745604.pdf [firstpage_image] =>[orig_patent_app_number] => 921022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2418669 [patent_doc_number] => 04761783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-02 [patent_title] => 'Apparatus and method for reporting occurrences of errors in signals stored in a data processor' [patent_app_type] => 1 [patent_app_number] => 6/920522 [patent_app_country] => US [patent_app_date] => 1986-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7093 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/761/04761783.pdf [firstpage_image] =>[orig_patent_app_number] => 920522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2484856 [patent_doc_number] => 04872168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-03 [patent_title] => 'Integrated circuit with memory self-test' [patent_app_type] => 1 [patent_app_number] => 6/914411 [patent_app_country] => US [patent_app_date] => 1986-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2804 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/872/04872168.pdf [firstpage_image] =>[orig_patent_app_number] => 914411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2498815 [patent_doc_number] => 04802167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-31 [patent_title] => 'Data monitor apparatus' [patent_app_type] => 1 [patent_app_number] => 6/914221 [patent_app_country] => US [patent_app_date] => 1986-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1933 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/802/04802167.pdf [firstpage_image] =>[orig_patent_app_number] => 914221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2397300 [patent_doc_number] => 04773071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-20 [patent_title] => 'Memory for storing response patterns in an automatic testing instrument' [patent_app_type] => 1 [patent_app_number] => 6/914440 [patent_app_country] => US [patent_app_date] => 1986-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3535 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/773/04773071.pdf [firstpage_image] =>[orig_patent_app_number] => 914440 [rel_patent_id] =>[rel_patent_doc_number] =>)