Search

Sara Elizabeth Townsley

Examiner (ID: 2446, Phone: (571)270-7672 , Office: P/1629 )

Most Active Art Unit
1629
Art Unit(s)
1629, 1612, 1613
Total Applications
514
Issued Applications
97
Pending Applications
81
Abandoned Applications
352

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2298853 [patent_doc_number] => 04710923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-01 [patent_title] => 'Control system for deinterleaving memories in digital audio reproducing apparatus' [patent_app_type] => 1 [patent_app_number] => 6/792890 [patent_app_country] => US [patent_app_date] => 1985-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5735 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/710/04710923.pdf [firstpage_image] =>[orig_patent_app_number] => 792890 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/792890
Control system for deinterleaving memories in digital audio reproducing apparatus Oct 29, 1985 Issued
Array ( [id] => 2424020 [patent_doc_number] => 04736376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-05 [patent_title] => 'Self-checking error correcting encoder/decoder' [patent_app_type] => 1 [patent_app_number] => 6/791321 [patent_app_country] => US [patent_app_date] => 1985-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 12497 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/736/04736376.pdf [firstpage_image] =>[orig_patent_app_number] => 791321 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/791321
Self-checking error correcting encoder/decoder Oct 24, 1985 Issued
Array ( [id] => 2341033 [patent_doc_number] => 04701921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-20 [patent_title] => 'Modularized scan path for serially tested logic circuit' [patent_app_type] => 1 [patent_app_number] => 6/790541 [patent_app_country] => US [patent_app_date] => 1985-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 10605 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/701/04701921.pdf [firstpage_image] =>[orig_patent_app_number] => 790541 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/790541
Modularized scan path for serially tested logic circuit Oct 22, 1985 Issued
Array ( [id] => 2298976 [patent_doc_number] => 04710931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-01 [patent_title] => 'Partitioned scan-testing system' [patent_app_type] => 1 [patent_app_number] => 6/790543 [patent_app_country] => US [patent_app_date] => 1985-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 10797 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/710/04710931.pdf [firstpage_image] =>[orig_patent_app_number] => 790543 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/790543
Partitioned scan-testing system Oct 22, 1985 Issued
Array ( [id] => 2299007 [patent_doc_number] => 04710933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-01 [patent_title] => 'Parallel/serial scan system for testing logic circuits' [patent_app_type] => 1 [patent_app_number] => 6/790569 [patent_app_country] => US [patent_app_date] => 1985-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 10630 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/710/04710933.pdf [firstpage_image] =>[orig_patent_app_number] => 790569 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/790569
Parallel/serial scan system for testing logic circuits Oct 22, 1985 Issued
Array ( [id] => 2331663 [patent_doc_number] => 04680762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-07-14 [patent_title] => 'Method and apparatus for locating soft cells in a ram' [patent_app_type] => 1 [patent_app_number] => 6/788443 [patent_app_country] => US [patent_app_date] => 1985-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5865 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/680/04680762.pdf [firstpage_image] =>[orig_patent_app_number] => 788443 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/788443
Method and apparatus for locating soft cells in a ram Oct 16, 1985 Issued
Array ( [id] => 2451726 [patent_doc_number] => 04722084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-01-26 [patent_title] => 'Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits' [patent_app_type] => 1 [patent_app_number] => 6/782850 [patent_app_country] => US [patent_app_date] => 1985-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8039 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/722/04722084.pdf [firstpage_image] =>[orig_patent_app_number] => 782850 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/782850
Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits Oct 1, 1985 Issued
Array ( [id] => 2305640 [patent_doc_number] => 04682328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-07-21 [patent_title] => 'Dynamic memory refresh and parity checking circuit' [patent_app_type] => 1 [patent_app_number] => 6/781023 [patent_app_country] => US [patent_app_date] => 1985-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3528 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/682/04682328.pdf [firstpage_image] =>[orig_patent_app_number] => 781023 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/781023
Dynamic memory refresh and parity checking circuit Sep 26, 1985 Issued
Array ( [id] => 2333902 [patent_doc_number] => 04706250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-11-10 [patent_title] => 'Method and apparatus for correcting multibyte errors having improved two-level code structure' [patent_app_type] => 1 [patent_app_number] => 6/781449 [patent_app_country] => US [patent_app_date] => 1985-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6582 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/706/04706250.pdf [firstpage_image] =>[orig_patent_app_number] => 781449 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/781449
Method and apparatus for correcting multibyte errors having improved two-level code structure Sep 26, 1985 Issued
Array ( [id] => 2459012 [patent_doc_number] => 04759020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-07-19 [patent_title] => 'Self-healing bubble memories' [patent_app_type] => 1 [patent_app_number] => 6/780129 [patent_app_country] => US [patent_app_date] => 1985-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2831 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/759/04759020.pdf [firstpage_image] =>[orig_patent_app_number] => 780129 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/780129
Self-healing bubble memories Sep 24, 1985 Issued
Array ( [id] => 2347015 [patent_doc_number] => 04713810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-15 [patent_title] => 'Diagnostic technique for determining fault locations within a digital transmission system' [patent_app_type] => 1 [patent_app_number] => 6/777803 [patent_app_country] => US [patent_app_date] => 1985-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2592 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/713/04713810.pdf [firstpage_image] =>[orig_patent_app_number] => 777803 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/777803
Diagnostic technique for determining fault locations within a digital transmission system Sep 18, 1985 Issued
Array ( [id] => 2298870 [patent_doc_number] => 04710924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-01 [patent_title] => 'Local and remote bit error rate monitoring for early warning of fault location of digital transmission system' [patent_app_type] => 1 [patent_app_number] => 6/777802 [patent_app_country] => US [patent_app_date] => 1985-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2584 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/710/04710924.pdf [firstpage_image] =>[orig_patent_app_number] => 777802 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/777802
Local and remote bit error rate monitoring for early warning of fault location of digital transmission system Sep 18, 1985 Issued
Array ( [id] => 2428624 [patent_doc_number] => 04727549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-02-23 [patent_title] => 'Watchdog activity monitor (WAM) for use wth high coverage processor self-test' [patent_app_type] => 1 [patent_app_number] => 6/758251 [patent_app_country] => US [patent_app_date] => 1985-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7250 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/727/04727549.pdf [firstpage_image] =>[orig_patent_app_number] => 758251 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/758251
Watchdog activity monitor (WAM) for use wth high coverage processor self-test Sep 12, 1985 Issued
Array ( [id] => 2363574 [patent_doc_number] => 04683570 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-07-28 [patent_title] => 'Self-checking digital fault detector for modular redundant real time clock' [patent_app_type] => 1 [patent_app_number] => 6/771852 [patent_app_country] => US [patent_app_date] => 1985-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3894 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/683/04683570.pdf [firstpage_image] =>[orig_patent_app_number] => 771852 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/771852
Self-checking digital fault detector for modular redundant real time clock Sep 2, 1985 Issued
Array ( [id] => 2341046 [patent_doc_number] => 04701922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-20 [patent_title] => 'Integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 6/769311 [patent_app_country] => US [patent_app_date] => 1985-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5224 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/701/04701922.pdf [firstpage_image] =>[orig_patent_app_number] => 769311 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/769311
Integrated circuit device Aug 25, 1985 Issued
Array ( [id] => 2355896 [patent_doc_number] => 04692921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-08 [patent_title] => 'Method for generating verification tests' [patent_app_type] => 1 [patent_app_number] => 6/768500 [patent_app_country] => US [patent_app_date] => 1985-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3889 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/692/04692921.pdf [firstpage_image] =>[orig_patent_app_number] => 768500 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/768500
Method for generating verification tests Aug 21, 1985 Issued
Array ( [id] => 2356536 [patent_doc_number] => 04703481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-27 [patent_title] => 'Method and apparatus for fault recovery within a computing system' [patent_app_type] => 1 [patent_app_number] => 6/766212 [patent_app_country] => US [patent_app_date] => 1985-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5629 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/703/04703481.pdf [firstpage_image] =>[orig_patent_app_number] => 766212 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/766212
Method and apparatus for fault recovery within a computing system Aug 15, 1985 Issued
Array ( [id] => 2331719 [patent_doc_number] => 04680765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-07-14 [patent_title] => 'Autosync circuit for error correcting block decoders' [patent_app_type] => 1 [patent_app_number] => 6/759252 [patent_app_country] => US [patent_app_date] => 1985-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2581 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/680/04680765.pdf [firstpage_image] =>[orig_patent_app_number] => 759252 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/759252
Autosync circuit for error correcting block decoders Jul 25, 1985 Issued
Array ( [id] => 2456662 [patent_doc_number] => 04723246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-02-02 [patent_title] => 'Integrated scrambler-encoder using PN sequence generator' [patent_app_type] => 1 [patent_app_number] => 6/759491 [patent_app_country] => US [patent_app_date] => 1985-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2108 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/723/04723246.pdf [firstpage_image] =>[orig_patent_app_number] => 759491 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/759491
Integrated scrambler-encoder using PN sequence generator Jul 24, 1985 Issued
Array ( [id] => 2270776 [patent_doc_number] => 04593395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-06-03 [patent_title] => 'Error correction method for the transfer of blocks of data bits, a device and performing such a method, a decoder for use with such a method, and a device comprising such a decoder' [patent_app_type] => 1 [patent_app_number] => 6/758587 [patent_app_country] => US [patent_app_date] => 1985-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5604 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 506 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/593/04593395.pdf [firstpage_image] =>[orig_patent_app_number] => 758587 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/758587
Error correction method for the transfer of blocks of data bits, a device and performing such a method, a decoder for use with such a method, and a device comprising such a decoder Jul 24, 1985 Issued
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