
Sara Elizabeth Townsley
Examiner (ID: 2446, Phone: (571)270-7672 , Office: P/1629 )
| Most Active Art Unit | 1629 |
| Art Unit(s) | 1629, 1612, 1613 |
| Total Applications | 514 |
| Issued Applications | 97 |
| Pending Applications | 81 |
| Abandoned Applications | 352 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2298265
[patent_doc_number] => 04639919
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-01-27
[patent_title] => 'Distributed pattern generator'
[patent_app_type] => 1
[patent_app_number] => 6/564853
[patent_app_country] => US
[patent_app_date] => 1983-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 12223
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/639/04639919.pdf
[firstpage_image] =>[orig_patent_app_number] => 564853
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/564853 | Distributed pattern generator | Dec 18, 1983 | Issued |
Array
(
[id] => 2243379
[patent_doc_number] => 04586183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-04-29
[patent_title] => 'Correcting errors in binary data'
[patent_app_type] => 1
[patent_app_number] => 6/561782
[patent_app_country] => US
[patent_app_date] => 1983-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 10532
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/586/04586183.pdf
[firstpage_image] =>[orig_patent_app_number] => 561782
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/561782 | Correcting errors in binary data | Dec 14, 1983 | Issued |
Array
(
[id] => 2240337
[patent_doc_number] => 04573155
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-02-25
[patent_title] => 'Maximum likelihood sequence decoder for linear cyclic codes'
[patent_app_type] => 1
[patent_app_number] => 6/561502
[patent_app_country] => US
[patent_app_date] => 1983-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3329
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/573/04573155.pdf
[firstpage_image] =>[orig_patent_app_number] => 561502
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/561502 | Maximum likelihood sequence decoder for linear cyclic codes | Dec 13, 1983 | Issued |
Array
(
[id] => 2266544
[patent_doc_number] => 04564941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-01-14
[patent_title] => 'Error detection system'
[patent_app_type] => 1
[patent_app_number] => 6/559210
[patent_app_country] => US
[patent_app_date] => 1983-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 4352
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/564/04564941.pdf
[firstpage_image] =>[orig_patent_app_number] => 559210
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/559210 | Error detection system | Dec 7, 1983 | Issued |
Array
(
[id] => 2205869
[patent_doc_number] => 04534028
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-08-06
[patent_title] => 'Random testing using scan path technique'
[patent_app_type] => 1
[patent_app_number] => 6/556812
[patent_app_country] => US
[patent_app_date] => 1983-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 5257
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 275
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/534/04534028.pdf
[firstpage_image] =>[orig_patent_app_number] => 556812
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/556812 | Random testing using scan path technique | Nov 30, 1983 | Issued |
Array
(
[id] => 2253849
[patent_doc_number] => 04606029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-08-12
[patent_title] => 'Data transmission system'
[patent_app_type] => 1
[patent_app_number] => 6/556860
[patent_app_country] => US
[patent_app_date] => 1983-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3758
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/606/04606029.pdf
[firstpage_image] =>[orig_patent_app_number] => 556860
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/556860 | Data transmission system | Nov 30, 1983 | Issued |
Array
(
[id] => 2352216
[patent_doc_number] => 04656632
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-04-07
[patent_title] => 'System for automatic testing of circuits and systems'
[patent_app_type] => 1
[patent_app_number] => 6/555287
[patent_app_country] => US
[patent_app_date] => 1983-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5169
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/656/04656632.pdf
[firstpage_image] =>[orig_patent_app_number] => 555287
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/555287 | System for automatic testing of circuits and systems | Nov 24, 1983 | Issued |
Array
(
[id] => 2292453
[patent_doc_number] => 04587654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-05-06
[patent_title] => 'System for processing machine check interruption'
[patent_app_type] => 1
[patent_app_number] => 6/554730
[patent_app_country] => US
[patent_app_date] => 1983-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2098
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/587/04587654.pdf
[firstpage_image] =>[orig_patent_app_number] => 554730
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/554730 | System for processing machine check interruption | Nov 22, 1983 | Issued |
Array
(
[id] => 2275800
[patent_doc_number] => 04584683
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-04-22
[patent_title] => 'Logic circuit test system'
[patent_app_type] => 1
[patent_app_number] => 6/554337
[patent_app_country] => US
[patent_app_date] => 1983-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4819
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/584/04584683.pdf
[firstpage_image] =>[orig_patent_app_number] => 554337
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/554337 | Logic circuit test system | Nov 21, 1983 | Issued |
Array
(
[id] => 2205456
[patent_doc_number] => 04542508
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-09-17
[patent_title] => 'Amenable logic gate and method of testing'
[patent_app_type] => 1
[patent_app_number] => 6/553571
[patent_app_country] => US
[patent_app_date] => 1983-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 8568
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/542/04542508.pdf
[firstpage_image] =>[orig_patent_app_number] => 553571
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/553571 | Amenable logic gate and method of testing | Nov 20, 1983 | Issued |
Array
(
[id] => 2125604
[patent_doc_number] => 04481629
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-11-06
[patent_title] => 'Abnormal signal detecting device'
[patent_app_type] => 1
[patent_app_number] => 6/552019
[patent_app_country] => US
[patent_app_date] => 1983-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 804
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/481/04481629.pdf
[firstpage_image] =>[orig_patent_app_number] => 552019
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/552019 | Abnormal signal detecting device | Nov 16, 1983 | Issued |
Array
(
[id] => 2205408
[patent_doc_number] => 04542505
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-09-17
[patent_title] => 'Adjustable system for skew comparison of digital signals'
[patent_app_type] => 1
[patent_app_number] => 6/551080
[patent_app_country] => US
[patent_app_date] => 1983-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6014
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/542/04542505.pdf
[firstpage_image] =>[orig_patent_app_number] => 551080
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/551080 | Adjustable system for skew comparison of digital signals | Nov 13, 1983 | Issued |
Array
(
[id] => 2241729
[patent_doc_number] => 04597080
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-06-24
[patent_title] => 'Architecture and method for testing VLSI processors'
[patent_app_type] => 1
[patent_app_number] => 6/551648
[patent_app_country] => US
[patent_app_date] => 1983-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5628
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/597/04597080.pdf
[firstpage_image] =>[orig_patent_app_number] => 551648
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/551648 | Architecture and method for testing VLSI processors | Nov 13, 1983 | Issued |
Array
(
[id] => 2283777
[patent_doc_number] => 04607365
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-08-19
[patent_title] => 'Fault-tolerant communications controller system'
[patent_app_type] => 1
[patent_app_number] => 6/551283
[patent_app_country] => US
[patent_app_date] => 1983-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4109
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/607/04607365.pdf
[firstpage_image] =>[orig_patent_app_number] => 551283
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/551283 | Fault-tolerant communications controller system | Nov 13, 1983 | Issued |
Array
(
[id] => 2318446
[patent_doc_number] => 04646300
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-02-24
[patent_title] => 'Communications method'
[patent_app_type] => 1
[patent_app_number] => 6/551297
[patent_app_country] => US
[patent_app_date] => 1983-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 6472
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/646/04646300.pdf
[firstpage_image] =>[orig_patent_app_number] => 551297
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/551297 | Communications method | Nov 13, 1983 | Issued |
Array
(
[id] => 2360941
[patent_doc_number] => 04651323
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-03-17
[patent_title] => 'Fault protection flip flop'
[patent_app_type] => 1
[patent_app_number] => 6/551302
[patent_app_country] => US
[patent_app_date] => 1983-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1418
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/651/04651323.pdf
[firstpage_image] =>[orig_patent_app_number] => 551302
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/551302 | Fault protection flip flop | Nov 13, 1983 | Issued |
Array
(
[id] => 2243346
[patent_doc_number] => 04586181
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-04-29
[patent_title] => 'Test pattern generating apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/551429
[patent_app_country] => US
[patent_app_date] => 1983-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 40
[patent_no_of_words] => 5780
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/586/04586181.pdf
[firstpage_image] =>[orig_patent_app_number] => 551429
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/551429 | Test pattern generating apparatus | Nov 13, 1983 | Issued |
Array
(
[id] => 2225991
[patent_doc_number] => 04594711
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-06-10
[patent_title] => 'Universal testing circuit and method'
[patent_app_type] => 1
[patent_app_number] => 6/551667
[patent_app_country] => US
[patent_app_date] => 1983-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6559
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/594/04594711.pdf
[firstpage_image] =>[orig_patent_app_number] => 551667
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/551667 | Universal testing circuit and method | Nov 9, 1983 | Issued |
Array
(
[id] => 2291369
[patent_doc_number] => 04604750
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-08-05
[patent_title] => 'Pipeline error correction'
[patent_app_type] => 1
[patent_app_number] => 6/549610
[patent_app_country] => US
[patent_app_date] => 1983-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3806
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/604/04604750.pdf
[firstpage_image] =>[orig_patent_app_number] => 549610
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/549610 | Pipeline error correction | Nov 6, 1983 | Issued |
Array
(
[id] => 2227727
[patent_doc_number] => 04583222
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-04-15
[patent_title] => 'Method and apparatus for self-testing of floating point accelerator processors'
[patent_app_type] => 1
[patent_app_number] => 6/549612
[patent_app_country] => US
[patent_app_date] => 1983-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4759
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/583/04583222.pdf
[firstpage_image] =>[orig_patent_app_number] => 549612
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/549612 | Method and apparatus for self-testing of floating point accelerator processors | Nov 6, 1983 | Issued |