
Sara Elizabeth Townsley
Examiner (ID: 2446, Phone: (571)270-7672 , Office: P/1629 )
| Most Active Art Unit | 1629 |
| Art Unit(s) | 1629, 1612, 1613 |
| Total Applications | 514 |
| Issued Applications | 97 |
| Pending Applications | 81 |
| Abandoned Applications | 352 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2094210
[patent_doc_number] => 04464747
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-08-07
[patent_title] => 'High reliability memory'
[patent_app_type] => 1
[patent_app_number] => 6/349873
[patent_app_country] => US
[patent_app_date] => 1982-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 7925
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/464/04464747.pdf
[firstpage_image] =>[orig_patent_app_number] => 349873
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/349873 | High reliability memory | Feb 17, 1982 | Issued |
Array
(
[id] => 2120920
[patent_doc_number] => 04468769
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-08-28
[patent_title] => 'Error correcting system for correcting two or three simultaneous errors in a code'
[patent_app_type] => 1
[patent_app_number] => 6/349319
[patent_app_country] => US
[patent_app_date] => 1982-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6851
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 331
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/468/04468769.pdf
[firstpage_image] =>[orig_patent_app_number] => 349319
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/349319 | Error correcting system for correcting two or three simultaneous errors in a code | Feb 15, 1982 | Issued |
Array
(
[id] => 2133648
[patent_doc_number] => 04454601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-06-12
[patent_title] => 'Method and apparatus for communication of information and error checking'
[patent_app_type] => 1
[patent_app_number] => 6/348524
[patent_app_country] => US
[patent_app_date] => 1982-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9360
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/454/04454601.pdf
[firstpage_image] =>[orig_patent_app_number] => 348524
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/348524 | Method and apparatus for communication of information and error checking | Feb 10, 1982 | Issued |
Array
(
[id] => 2096714
[patent_doc_number] => 04486883
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-12-04
[patent_title] => 'Address check system'
[patent_app_type] => 1
[patent_app_number] => 6/345404
[patent_app_country] => US
[patent_app_date] => 1982-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1130
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/486/04486883.pdf
[firstpage_image] =>[orig_patent_app_number] => 345404
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/345404 | Address check system | Feb 2, 1982 | Issued |
Array
(
[id] => 2089883
[patent_doc_number] => 04435807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-03-06
[patent_title] => 'Orchard error correction system'
[patent_app_type] => 1
[patent_app_number] => 6/343109
[patent_app_country] => US
[patent_app_date] => 1982-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 22
[patent_no_of_words] => 6739
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/435/04435807.pdf
[firstpage_image] =>[orig_patent_app_number] => 343109
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/343109 | Orchard error correction system | Jan 26, 1982 | Issued |
Array
(
[id] => 2071399
[patent_doc_number] => 04459693
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-07-10
[patent_title] => 'Method of and apparatus for the automatic diagnosis of the failure of electrical devices connected to common bus nodes and the like'
[patent_app_type] => 1
[patent_app_number] => 6/342902
[patent_app_country] => US
[patent_app_date] => 1982-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4654
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/459/04459693.pdf
[firstpage_image] =>[orig_patent_app_number] => 342902
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/342902 | Method of and apparatus for the automatic diagnosis of the failure of electrical devices connected to common bus nodes and the like | Jan 25, 1982 | Issued |
Array
(
[id] => 2072652
[patent_doc_number] => 04430737
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-02-07
[patent_title] => 'Exclusive or circuit and parity checking circuit incorporating the same'
[patent_app_type] => 1
[patent_app_number] => 6/342875
[patent_app_country] => US
[patent_app_date] => 1982-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5768
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/430/04430737.pdf
[firstpage_image] =>[orig_patent_app_number] => 342875
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/342875 | Exclusive or circuit and parity checking circuit incorporating the same | Jan 25, 1982 | Issued |
Array
(
[id] => 2079835
[patent_doc_number] => 04461002
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-07-17
[patent_title] => 'Digital signal receiver'
[patent_app_type] => 1
[patent_app_number] => 6/340829
[patent_app_country] => US
[patent_app_date] => 1982-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 19
[patent_no_of_words] => 9918
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/461/04461002.pdf
[firstpage_image] =>[orig_patent_app_number] => 340829
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/340829 | Digital signal receiver | Jan 18, 1982 | Issued |
Array
(
[id] => 2115975
[patent_doc_number] => 04451922
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-05-29
[patent_title] => 'Transmission logic parity circuit'
[patent_app_type] => 1
[patent_app_number] => 6/332706
[patent_app_country] => US
[patent_app_date] => 1981-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 4084
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 641
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/451/04451922.pdf
[firstpage_image] =>[orig_patent_app_number] => 332706
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/332706 | Transmission logic parity circuit | Dec 20, 1981 | Issued |
Array
(
[id] => 2099011
[patent_doc_number] => 04456995
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-06-26
[patent_title] => 'Apparatus for high speed fault mapping of large memories'
[patent_app_type] => 1
[patent_app_number] => 6/345944
[patent_app_country] => US
[patent_app_date] => 1981-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3718
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/456/04456995.pdf
[firstpage_image] =>[orig_patent_app_number] => 345944
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/345944 | Apparatus for high speed fault mapping of large memories | Dec 17, 1981 | Issued |
Array
(
[id] => 2065710
[patent_doc_number] => 04428076
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-01-24
[patent_title] => 'Method of and system for evaluating bit errors in testing a signal path'
[patent_app_type] => 1
[patent_app_number] => 6/330719
[patent_app_country] => US
[patent_app_date] => 1981-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2197
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/428/04428076.pdf
[firstpage_image] =>[orig_patent_app_number] => 330719
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/330719 | Method of and system for evaluating bit errors in testing a signal path | Dec 13, 1981 | Issued |
Array
(
[id] => 2042094
[patent_doc_number] => 04414667
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1983-11-08
[patent_title] => 'Forward error correcting apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/325606
[patent_app_country] => US
[patent_app_date] => 1981-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 27
[patent_no_of_words] => 5742
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 604
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/414/04414667.pdf
[firstpage_image] =>[orig_patent_app_number] => 325606
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/325606 | Forward error correcting apparatus | Nov 26, 1981 | Issued |
Array
(
[id] => 2066585
[patent_doc_number] => 04453250
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-06-05
[patent_title] => 'PCM Signal processing apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/324815
[patent_app_country] => US
[patent_app_date] => 1981-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4343
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/453/04453250.pdf
[firstpage_image] =>[orig_patent_app_number] => 324815
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/324815 | PCM Signal processing apparatus | Nov 24, 1981 | Issued |
Array
(
[id] => 2115944
[patent_doc_number] => 04451920
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-05-29
[patent_title] => 'PCM Signal processing apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/324816
[patent_app_country] => US
[patent_app_date] => 1981-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4643
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/451/04451920.pdf
[firstpage_image] =>[orig_patent_app_number] => 324816
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/324816 | PCM Signal processing apparatus | Nov 24, 1981 | Issued |
| 06/323809 | ERROR CORRECTING CODE DECODER | Nov 22, 1981 | Abandoned |
Array
(
[id] => 2078295
[patent_doc_number] => 04471483
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-09-11
[patent_title] => 'Branched labyrinth wafer-scale integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 6/322117
[patent_app_country] => US
[patent_app_date] => 1981-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 38
[patent_no_of_words] => 12357
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/471/04471483.pdf
[firstpage_image] =>[orig_patent_app_number] => 322117
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/322117 | Branched labyrinth wafer-scale integrated circuit | Nov 16, 1981 | Issued |
Array
(
[id] => 2211859
[patent_doc_number] => 04493082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-01-08
[patent_title] => 'Soft decision convolutional code transmission systems'
[patent_app_type] => 1
[patent_app_number] => 6/320923
[patent_app_country] => US
[patent_app_date] => 1981-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 3952
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/493/04493082.pdf
[firstpage_image] =>[orig_patent_app_number] => 320923
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/320923 | Soft decision convolutional code transmission systems | Nov 12, 1981 | Issued |
Array
(
[id] => 2043077
[patent_doc_number] => 04413340
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1983-11-01
[patent_title] => 'Error correctable data transmission method'
[patent_app_type] => 1
[patent_app_number] => 6/320492
[patent_app_country] => US
[patent_app_date] => 1981-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 6700
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/413/04413340.pdf
[firstpage_image] =>[orig_patent_app_number] => 320492
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/320492 | Error correctable data transmission method | Nov 11, 1981 | Issued |
Array
(
[id] => 2106701
[patent_doc_number] => 04442520
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-04-10
[patent_title] => 'Signal error detecting'
[patent_app_type] => 1
[patent_app_number] => 6/317295
[patent_app_country] => US
[patent_app_date] => 1981-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2940
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/442/04442520.pdf
[firstpage_image] =>[orig_patent_app_number] => 317295
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/317295 | Signal error detecting | Nov 1, 1981 | Issued |
Array
(
[id] => 2125584
[patent_doc_number] => 04481627
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-11-06
[patent_title] => 'Embedded memory testing method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/316720
[patent_app_country] => US
[patent_app_date] => 1981-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 8193
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/481/04481627.pdf
[firstpage_image] =>[orig_patent_app_number] => 316720
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/316720 | Embedded memory testing method and apparatus | Oct 29, 1981 | Issued |