Search

Sara Elizabeth Townsley

Examiner (ID: 2446, Phone: (571)270-7672 , Office: P/1629 )

Most Active Art Unit
1629
Art Unit(s)
1629, 1612, 1613
Total Applications
514
Issued Applications
97
Pending Applications
81
Abandoned Applications
352

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1976812 [patent_doc_number] => 04365333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-12-21 [patent_title] => 'Test signal generator' [patent_app_type] => 1 [patent_app_number] => 6/189395 [patent_app_country] => US [patent_app_date] => 1980-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4214 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/365/04365333.pdf [firstpage_image] =>[orig_patent_app_number] => 189395 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/189395
Test signal generator Sep 21, 1980 Issued
Array ( [id] => 1954078 [patent_doc_number] => 04355390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-19 [patent_title] => 'Method for checking data written into buffered write-read memories in numerically controlled machine tools' [patent_app_type] => 1 [patent_app_number] => 6/189110 [patent_app_country] => US [patent_app_date] => 1980-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 903 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/355/04355390.pdf [firstpage_image] =>[orig_patent_app_number] => 189110 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/189110
Method for checking data written into buffered write-read memories in numerically controlled machine tools Sep 21, 1980 Issued
Array ( [id] => 2033398 [patent_doc_number] => 04377863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-03-22 [patent_title] => 'Synchronization loss tolerant cyclic error checking method and apparatus' [patent_app_type] => 1 [patent_app_number] => 6/184661 [patent_app_country] => US [patent_app_date] => 1980-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2858 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/377/04377863.pdf [firstpage_image] =>[orig_patent_app_number] => 184661 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/184661
Synchronization loss tolerant cyclic error checking method and apparatus Sep 7, 1980 Issued
Array ( [id] => 1975933 [patent_doc_number] => 04354269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-12 [patent_title] => 'Apparatus for the processing of an information stream with the aid of an error-correcting convolutional code and apparatus for the detection of an error still irremediable in this processing' [patent_app_type] => 1 [patent_app_number] => 6/185050 [patent_app_country] => US [patent_app_date] => 1980-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 11211 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 470 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/354/04354269.pdf [firstpage_image] =>[orig_patent_app_number] => 185050 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/185050
Apparatus for the processing of an information stream with the aid of an error-correcting convolutional code and apparatus for the detection of an error still irremediable in this processing Sep 7, 1980 Issued
Array ( [id] => 2055689 [patent_doc_number] => 04390990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-06-28 [patent_title] => 'Method for multiple signal collision detection on a transmission line' [patent_app_type] => 1 [patent_app_number] => 6/184855 [patent_app_country] => US [patent_app_date] => 1980-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 532 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/390/04390990.pdf [firstpage_image] =>[orig_patent_app_number] => 184855 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/184855
Method for multiple signal collision detection on a transmission line Sep 7, 1980 Issued
Array ( [id] => 1982253 [patent_doc_number] => 04328583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-05-04 [patent_title] => 'Data bus fault detector' [patent_app_type] => 1 [patent_app_number] => 6/185118 [patent_app_country] => US [patent_app_date] => 1980-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2728 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/328/04328583.pdf [firstpage_image] =>[orig_patent_app_number] => 185118 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/185118
Data bus fault detector Sep 7, 1980 Issued
Array ( [id] => 1949764 [patent_doc_number] => 04342112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-07-27 [patent_title] => 'Error checking circuit' [patent_app_type] => 1 [patent_app_number] => 6/185119 [patent_app_country] => US [patent_app_date] => 1980-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2299 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/342/04342112.pdf [firstpage_image] =>[orig_patent_app_number] => 185119 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/185119
Error checking circuit Sep 7, 1980 Issued
06/251533 GO/NO GO MARGIN TEST CIRCUIT FOR SEMICONDUCTOR MEMORY Sep 7, 1980 Abandoned
Array ( [id] => 1962294 [patent_doc_number] => 04358847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-11-09 [patent_title] => 'Electrical circuit test apparatus and method' [patent_app_type] => 1 [patent_app_number] => 6/183367 [patent_app_country] => US [patent_app_date] => 1980-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3136 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/358/04358847.pdf [firstpage_image] =>[orig_patent_app_number] => 183367 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/183367
Electrical circuit test apparatus and method Sep 1, 1980 Issued
Array ( [id] => 1943408 [patent_doc_number] => 04340940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-07-20 [patent_title] => 'Hardware reduction by truncation of selected number of most significant bits for digital video system using subsampling and adaptive reconstruction' [patent_app_type] => 1 [patent_app_number] => 6/181425 [patent_app_country] => US [patent_app_date] => 1980-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2223 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/340/04340940.pdf [firstpage_image] =>[orig_patent_app_number] => 181425 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/181425
Hardware reduction by truncation of selected number of most significant bits for digital video system using subsampling and adaptive reconstruction Aug 25, 1980 Issued
Array ( [id] => 1960429 [patent_doc_number] => 04339820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-07-13 [patent_title] => 'Method and device for coding and/or decoding and securing data' [patent_app_type] => 1 [patent_app_number] => 6/179710 [patent_app_country] => US [patent_app_date] => 1980-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2197 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/339/04339820.pdf [firstpage_image] =>[orig_patent_app_number] => 179710 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/179710
Method and device for coding and/or decoding and securing data Aug 19, 1980 Issued
Array ( [id] => 1934872 [patent_doc_number] => 04347609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-08-31 [patent_title] => 'Method and system for transmission of serial data' [patent_app_type] => 1 [patent_app_number] => 6/179935 [patent_app_country] => US [patent_app_date] => 1980-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4618 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/347/04347609.pdf [firstpage_image] =>[orig_patent_app_number] => 179935 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/179935
Method and system for transmission of serial data Aug 19, 1980 Issued
Array ( [id] => 1988111 [patent_doc_number] => 04360918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-11-23 [patent_title] => 'Arrangement for detecting defects during the asynchronous transfer of digital measured values' [patent_app_type] => 1 [patent_app_number] => 6/179355 [patent_app_country] => US [patent_app_date] => 1980-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1894 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/360/04360918.pdf [firstpage_image] =>[orig_patent_app_number] => 179355 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/179355
Arrangement for detecting defects during the asynchronous transfer of digital measured values Aug 17, 1980 Issued
Array ( [id] => 2028969 [patent_doc_number] => 04376977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-03-15 [patent_title] => 'Computer system with scannable program memory' [patent_app_type] => 1 [patent_app_number] => 6/178646 [patent_app_country] => US [patent_app_date] => 1980-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10103 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/376/04376977.pdf [firstpage_image] =>[orig_patent_app_number] => 178646 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/178646
Computer system with scannable program memory Aug 14, 1980 Issued
Array ( [id] => 1977995 [patent_doc_number] => 04348762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-09-07 [patent_title] => 'Circuit for correcting data reading clock pulses' [patent_app_type] => 1 [patent_app_number] => 6/176974 [patent_app_country] => US [patent_app_date] => 1980-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1664 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/348/04348762.pdf [firstpage_image] =>[orig_patent_app_number] => 176974 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/176974
Circuit for correcting data reading clock pulses Aug 10, 1980 Issued
Array ( [id] => 1949626 [patent_doc_number] => 04342084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-07-27 [patent_title] => 'Main storage validation means' [patent_app_type] => 1 [patent_app_number] => 6/176827 [patent_app_country] => US [patent_app_date] => 1980-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 10306 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/342/04342084.pdf [firstpage_image] =>[orig_patent_app_number] => 176827 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/176827
Main storage validation means Aug 10, 1980 Issued
Array ( [id] => 1968677 [patent_doc_number] => 04320506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-03-16 [patent_title] => 'Apparatus and method for simulation testing of an anti-block system' [patent_app_type] => 1 [patent_app_number] => 6/177079 [patent_app_country] => US [patent_app_date] => 1980-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3444 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/320/04320506.pdf [firstpage_image] =>[orig_patent_app_number] => 177079 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/177079
Apparatus and method for simulation testing of an anti-block system Aug 10, 1980 Issued
Array ( [id] => 1941281 [patent_doc_number] => 04335457 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-06-15 [patent_title] => 'Method for semiconductor memory testing' [patent_app_type] => 1 [patent_app_number] => 6/176353 [patent_app_country] => US [patent_app_date] => 1980-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2513 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/335/04335457.pdf [firstpage_image] =>[orig_patent_app_number] => 176353 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/176353
Method for semiconductor memory testing Aug 7, 1980 Issued
Array ( [id] => 1988438 [patent_doc_number] => 04346472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-08-24 [patent_title] => 'Method and apparatus for eliminating double bit errosion in a differential phase shift keying system' [patent_app_type] => 1 [patent_app_number] => 6/176205 [patent_app_country] => US [patent_app_date] => 1980-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2617 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/346/04346472.pdf [firstpage_image] =>[orig_patent_app_number] => 176205 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/176205
Method and apparatus for eliminating double bit errosion in a differential phase shift keying system Aug 6, 1980 Issued
Array ( [id] => 2009600 [patent_doc_number] => 04368532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-01-11 [patent_title] => 'Memory checking method' [patent_app_type] => 1 [patent_app_number] => 6/173726 [patent_app_country] => US [patent_app_date] => 1980-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4551 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/368/04368532.pdf [firstpage_image] =>[orig_patent_app_number] => 173726 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/173726
Memory checking method Jul 29, 1980 Issued
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