
Sara Elizabeth Townsley
Examiner (ID: 2446, Phone: (571)270-7672 , Office: P/1629 )
| Most Active Art Unit | 1629 |
| Art Unit(s) | 1629, 1612, 1613 |
| Total Applications | 514 |
| Issued Applications | 97 |
| Pending Applications | 81 |
| Abandoned Applications | 352 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2956605
[patent_doc_number] => 05255272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-19
[patent_title] => 'Predictive tape drive error correction apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/660652
[patent_app_country] => US
[patent_app_date] => 1991-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3622
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/255/05255272.pdf
[firstpage_image] =>[orig_patent_app_number] => 660652
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/660652 | Predictive tape drive error correction apparatus | Feb 24, 1991 | Issued |
Array
(
[id] => 2988090
[patent_doc_number] => 05257267
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Variable length scan string and cell for same'
[patent_app_type] => 1
[patent_app_number] => 7/660532
[patent_app_country] => US
[patent_app_date] => 1991-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 2983
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/257/05257267.pdf
[firstpage_image] =>[orig_patent_app_number] => 660532
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/660532 | Variable length scan string and cell for same | Feb 24, 1991 | Issued |
Array
(
[id] => 2950196
[patent_doc_number] => 05191584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-02
[patent_title] => 'Mass storage array with efficient parity calculation'
[patent_app_type] => 1
[patent_app_number] => 7/658317
[patent_app_country] => US
[patent_app_date] => 1991-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2413
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/191/05191584.pdf
[firstpage_image] =>[orig_patent_app_number] => 658317
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/658317 | Mass storage array with efficient parity calculation | Feb 19, 1991 | Issued |
Array
(
[id] => 2958800
[patent_doc_number] => 05255385
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-19
[patent_title] => 'Method of testing program, and compiler and program testing tool for the method'
[patent_app_type] => 1
[patent_app_number] => 7/658222
[patent_app_country] => US
[patent_app_date] => 1991-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 51
[patent_no_of_words] => 6514
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/255/05255385.pdf
[firstpage_image] =>[orig_patent_app_number] => 658222
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/658222 | Method of testing program, and compiler and program testing tool for the method | Feb 19, 1991 | Issued |
Array
(
[id] => 3062284
[patent_doc_number] => 05325376
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-28
[patent_title] => 'Communication system for detecting a communication error in information transmitted between a plurality of units and a main control unit'
[patent_app_type] => 1
[patent_app_number] => 7/658391
[patent_app_country] => US
[patent_app_date] => 1991-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
[patent_figures_cnt] => 55
[patent_no_of_words] => 15888
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/325/05325376.pdf
[firstpage_image] =>[orig_patent_app_number] => 658391
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/658391 | Communication system for detecting a communication error in information transmitted between a plurality of units and a main control unit | Feb 19, 1991 | Issued |
| 07/657172 | METHOD AND APPARATUS FOR HIGH SPEED PARALLEL COMMUNICATIONS | Feb 18, 1991 | Abandoned |
| 07/658415 | METHOD FOR AUTOMATIC ISOLATION OF FUNCTIONAL BLOCKS WITHIN INTEGRATED CIRCUITS | Feb 14, 1991 | Abandoned |
Array
(
[id] => 3106750
[patent_doc_number] => 05369756
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Fault tree displaying method and process diagnosis support system'
[patent_app_type] => 1
[patent_app_number] => 7/642892
[patent_app_country] => US
[patent_app_date] => 1991-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 7705
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/369/05369756.pdf
[firstpage_image] =>[orig_patent_app_number] => 642892
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/642892 | Fault tree displaying method and process diagnosis support system | Jan 17, 1991 | Issued |
Array
(
[id] => 2913836
[patent_doc_number] => 05249186
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-28
[patent_title] => 'Apparatus for detecting the start of frame in bipolar transmission systems'
[patent_app_type] => 1
[patent_app_number] => 7/642262
[patent_app_country] => US
[patent_app_date] => 1991-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4692
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/249/05249186.pdf
[firstpage_image] =>[orig_patent_app_number] => 642262
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/642262 | Apparatus for detecting the start of frame in bipolar transmission systems | Jan 15, 1991 | Issued |
Array
(
[id] => 2841445
[patent_doc_number] => 05128944
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-07
[patent_title] => 'Apparatus and method for providing notification of bit-cell failure in a redundant-bit-cell memory'
[patent_app_type] => 1
[patent_app_number] => 7/639737
[patent_app_country] => US
[patent_app_date] => 1991-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3168
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/128/05128944.pdf
[firstpage_image] =>[orig_patent_app_number] => 639737
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/639737 | Apparatus and method for providing notification of bit-cell failure in a redundant-bit-cell memory | Jan 10, 1991 | Issued |
Array
(
[id] => 2984323
[patent_doc_number] => 05195095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-16
[patent_title] => 'Algorithm for identifying tests to perform for fault isolation'
[patent_app_type] => 1
[patent_app_number] => 7/635442
[patent_app_country] => US
[patent_app_date] => 1990-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 7680
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 264
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/195/05195095.pdf
[firstpage_image] =>[orig_patent_app_number] => 635442
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/635442 | Algorithm for identifying tests to perform for fault isolation | Dec 27, 1990 | Issued |
Array
(
[id] => 2986779
[patent_doc_number] => 05226043
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-06
[patent_title] => 'Apparatus and method for data error detection and correction and address error detection in a memory system'
[patent_app_type] => 1
[patent_app_number] => 7/634632
[patent_app_country] => US
[patent_app_date] => 1990-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6223
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 125
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/226/05226043.pdf
[firstpage_image] =>[orig_patent_app_number] => 634632
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/634632 | Apparatus and method for data error detection and correction and address error detection in a memory system | Dec 26, 1990 | Issued |
Array
(
[id] => 2958618
[patent_doc_number] => 05222066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-22
[patent_title] => 'Modular self-test for embedded SRAMS'
[patent_app_type] => 1
[patent_app_number] => 7/633862
[patent_app_country] => US
[patent_app_date] => 1990-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 5960
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 199
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/222/05222066.pdf
[firstpage_image] =>[orig_patent_app_number] => 633862
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/633862 | Modular self-test for embedded SRAMS | Dec 25, 1990 | Issued |
Array
(
[id] => 2932584
[patent_doc_number] => 05235601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-10
[patent_title] => 'On-line restoration of redundancy information in a redundant array system'
[patent_app_type] => 1
[patent_app_number] => 7/632182
[patent_app_country] => US
[patent_app_date] => 1990-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4719
[patent_no_of_claims] => 30
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/235/05235601.pdf
[firstpage_image] =>[orig_patent_app_number] => 632182
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/632182 | On-line restoration of redundancy information in a redundant array system | Dec 20, 1990 | Issued |
Array
(
[id] => 2956120
[patent_doc_number] => 05181203
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-19
[patent_title] => 'Testable power-on-reset circuit'
[patent_app_type] => 1
[patent_app_number] => 7/631544
[patent_app_country] => US
[patent_app_date] => 1990-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1812
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/181/05181203.pdf
[firstpage_image] =>[orig_patent_app_number] => 631544
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/631544 | Testable power-on-reset circuit | Dec 20, 1990 | Issued |
Array
(
[id] => 2744510
[patent_doc_number] => 05077742
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Error-corrected facsimile communication control system'
[patent_app_type] => 1
[patent_app_number] => 7/630755
[patent_app_country] => US
[patent_app_date] => 1990-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 8277
[patent_no_of_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/077/05077742.pdf
[firstpage_image] =>[orig_patent_app_number] => 630755
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/630755 | Error-corrected facsimile communication control system | Dec 20, 1990 | Issued |
Array
(
[id] => 2986873
[patent_doc_number] => 05226048
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-06
[patent_title] => 'At-speed testing of core logic'
[patent_app_type] => 1
[patent_app_number] => 7/632012
[patent_app_country] => US
[patent_app_date] => 1990-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2908
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/226/05226048.pdf
[firstpage_image] =>[orig_patent_app_number] => 632012
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/632012 | At-speed testing of core logic | Dec 20, 1990 | Issued |
Array
(
[id] => 3075985
[patent_doc_number] => 05295141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-15
[patent_title] => 'Sensing and responding to invalid states in logic circuitry'
[patent_app_type] => 1
[patent_app_number] => 7/629802
[patent_app_country] => US
[patent_app_date] => 1990-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3187
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/295/05295141.pdf
[firstpage_image] =>[orig_patent_app_number] => 629802
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/629802 | Sensing and responding to invalid states in logic circuitry | Dec 18, 1990 | Issued |
Array
(
[id] => 2929477
[patent_doc_number] => 05206865
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-27
[patent_title] => 'Error detection and correction memory system'
[patent_app_type] => 1
[patent_app_number] => 7/628502
[patent_app_country] => US
[patent_app_date] => 1990-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 1808
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[pdf_file] => patents/05/206/05206865.pdf
[firstpage_image] =>[orig_patent_app_number] => 628502
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/628502 | Error detection and correction memory system | Dec 16, 1990 | Issued |
Array
(
[id] => 2949055
[patent_doc_number] => 05260949
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Scan path system and an integrated circuit device using the same'
[patent_app_type] => 1
[patent_app_number] => 7/628688
[patent_app_country] => US
[patent_app_date] => 1990-12-14
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/260/05260949.pdf
[firstpage_image] =>[orig_patent_app_number] => 628688
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/628688 | Scan path system and an integrated circuit device using the same | Dec 13, 1990 | Issued |