Search

Sara W. Crane

Examiner (ID: 10283)

Most Active Art Unit
2811
Art Unit(s)
2503, 2811, 2508, 2899
Total Applications
1624
Issued Applications
1262
Pending Applications
54
Abandoned Applications
308

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4264729 [patent_doc_number] => 06204532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Pillar transistor incorporating a body contact' [patent_app_type] => 1 [patent_app_number] => 9/412866 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 44 [patent_no_of_words] => 6048 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204532.pdf [firstpage_image] =>[orig_patent_app_number] => 412866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412866
Pillar transistor incorporating a body contact Oct 4, 1999 Issued
Array ( [id] => 1587890 [patent_doc_number] => 06359326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Composite transistor incorporating collector-common resistors' [patent_app_type] => B1 [patent_app_number] => 09/401724 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5345 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359326.pdf [firstpage_image] =>[orig_patent_app_number] => 09401724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401724
Composite transistor incorporating collector-common resistors Sep 22, 1999 Issued
Array ( [id] => 1542486 [patent_doc_number] => 06372555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor integrated circuit device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/399926 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2843 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372555.pdf [firstpage_image] =>[orig_patent_app_number] => 09399926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399926
Semiconductor integrated circuit device and method of manufacturing the same Sep 20, 1999 Issued
Array ( [id] => 1571195 [patent_doc_number] => 06498385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Post-fuse blow corrosion prevention structure for copper fuses' [patent_app_type] => B1 [patent_app_number] => 09/388314 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 8882 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498385.pdf [firstpage_image] =>[orig_patent_app_number] => 09388314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388314
Post-fuse blow corrosion prevention structure for copper fuses Aug 31, 1999 Issued
Array ( [id] => 1390839 [patent_doc_number] => 06552378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Ultra compact DRAM cell and method of making' [patent_app_type] => B1 [patent_app_number] => 09/385931 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5217 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552378.pdf [firstpage_image] =>[orig_patent_app_number] => 09385931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385931
Ultra compact DRAM cell and method of making Aug 29, 1999 Issued
Array ( [id] => 4319799 [patent_doc_number] => 06242790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Using polysilicon fuse for IC programming' [patent_app_type] => 1 [patent_app_number] => 9/385550 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4058 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242790.pdf [firstpage_image] =>[orig_patent_app_number] => 385550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385550
Using polysilicon fuse for IC programming Aug 29, 1999 Issued
Array ( [id] => 6137930 [patent_doc_number] => 20020000637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'MONOLITHIC INTEGRATED CIRCUIT WITH SEVERAL CAPACITORS FORMING BYPASS TO GROUND' [patent_app_type] => new [patent_app_number] => 09/384125 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1594 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000637.pdf [firstpage_image] =>[orig_patent_app_number] => 09384125 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384125
Monolithic integrated circuit with several capacitors forming bypass to ground Aug 26, 1999 Issued
Array ( [id] => 1138357 [patent_doc_number] => 06780745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Semiconductor integrated circuit and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/377740 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2999 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780745.pdf [firstpage_image] =>[orig_patent_app_number] => 09377740 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377740
Semiconductor integrated circuit and method of manufacturing the same Aug 19, 1999 Issued
09/376695 SENSING DEVICES USING CHEMICALLY-GATED SINGLE ELECTRON TRANSISTORS Aug 17, 1999 Abandoned
Array ( [id] => 1544307 [patent_doc_number] => 06373118 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'High-value integrated circuit resistor' [patent_app_type] => B1 [patent_app_number] => 09/372546 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4395 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373118.pdf [firstpage_image] =>[orig_patent_app_number] => 09372546 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372546
High-value integrated circuit resistor Aug 10, 1999 Issued
Array ( [id] => 4362650 [patent_doc_number] => 06175140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Semiconductor device using a shallow trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/372043 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 5577 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175140.pdf [firstpage_image] =>[orig_patent_app_number] => 372043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372043
Semiconductor device using a shallow trench isolation Aug 10, 1999 Issued
Array ( [id] => 4360826 [patent_doc_number] => 06218718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Spin transistor' [patent_app_type] => 1 [patent_app_number] => 9/171776 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3635 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218718.pdf [firstpage_image] =>[orig_patent_app_number] => 171776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/171776
Spin transistor Aug 1, 1999 Issued
Array ( [id] => 4424623 [patent_doc_number] => 06225652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Vertical laser fuse structure allowing increased packing density' [patent_app_type] => 1 [patent_app_number] => 9/365494 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4216 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225652.pdf [firstpage_image] =>[orig_patent_app_number] => 365494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365494
Vertical laser fuse structure allowing increased packing density Aug 1, 1999 Issued
Array ( [id] => 1463659 [patent_doc_number] => 06351008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions' [patent_app_type] => B1 [patent_app_number] => 09/359336 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 4571 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351008.pdf [firstpage_image] =>[orig_patent_app_number] => 09359336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359336
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions Jul 20, 1999 Issued
Array ( [id] => 4309797 [patent_doc_number] => 06188124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Semiconductor arrangement preventing damage during contact processing' [patent_app_type] => 1 [patent_app_number] => 9/354374 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188124.pdf [firstpage_image] =>[orig_patent_app_number] => 354374 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354374
Semiconductor arrangement preventing damage during contact processing Jul 13, 1999 Issued
Array ( [id] => 1380117 [patent_doc_number] => 06563187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'CMOS image sensor integrated together with memory device' [patent_app_type] => B1 [patent_app_number] => 09/342343 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1954 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563187.pdf [firstpage_image] =>[orig_patent_app_number] => 09342343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342343
CMOS image sensor integrated together with memory device Jun 28, 1999 Issued
Array ( [id] => 6897441 [patent_doc_number] => 20010045606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => new [patent_app_number] => 09/342751 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20010045606.pdf [firstpage_image] =>[orig_patent_app_number] => 09342751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342751
Semiconductor device with self-aligned areas formed using a supplemental silicon overlayer Jun 28, 1999 Issued
Array ( [id] => 4282216 [patent_doc_number] => 06281532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering' [patent_app_type] => 1 [patent_app_number] => 9/340954 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3443 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281532.pdf [firstpage_image] =>[orig_patent_app_number] => 340954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340954
Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering Jun 27, 1999 Issued
Array ( [id] => 4333670 [patent_doc_number] => 06320238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Gate structure for integrated circuit fabrication' [patent_app_type] => 1 [patent_app_number] => 9/339895 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3501 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320238.pdf [firstpage_image] =>[orig_patent_app_number] => 339895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339895
Gate structure for integrated circuit fabrication Jun 24, 1999 Issued
Array ( [id] => 4388081 [patent_doc_number] => 06278159 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor' [patent_app_type] => 1 [patent_app_number] => 9/344426 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3042 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278159.pdf [firstpage_image] =>[orig_patent_app_number] => 344426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344426
Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor Jun 24, 1999 Issued
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