Sara W. Crane

Array ( [id] => 4282354 [patent_doc_number] => 06281542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Flower-like capacitor structure for a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/249840 [patent_app_country] => US [patent_app_date] => 1999-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2848 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281542.pdf [firstpage_image] =>[orig_patent_app_number] => 249840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524825 [patent_doc_number] => 06353234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Layered arrangement and component containing the latter' [patent_app_type] => B1 [patent_app_number] => 09/242366 [patent_app_country] => US [patent_app_date] => 1999-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2271 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353234.pdf [firstpage_image] =>[orig_patent_app_number] => 09242366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1500245 [patent_doc_number] => 06486014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/246014 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 6703 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486014.pdf [firstpage_image] =>[orig_patent_app_number] => 09246014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1509210 [patent_doc_number] => 06441395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Column-row addressable electric microswitch arrays and sensor matrices employing them' [patent_app_type] => B1 [patent_app_number] => 09/241656 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 10445 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441395.pdf [firstpage_image] =>[orig_patent_app_number] => 09241656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301048 [patent_doc_number] => 06184557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection' [patent_app_type] => 1 [patent_app_number] => 9/239344 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4159 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184557.pdf [firstpage_image] =>[orig_patent_app_number] => 239344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4355263 [patent_doc_number] => 06215153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'MOSFET and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/235747 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2207 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215153.pdf [firstpage_image] =>[orig_patent_app_number] => 235747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4321771 [patent_doc_number] => 06331463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method for manufacturing low power high efficiency non-volatile erasable programmable memory cell structure' [patent_app_type] => 1 [patent_app_number] => 9/233375 [patent_app_country] => US [patent_app_date] => 1999-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3020 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331463.pdf [firstpage_image] =>[orig_patent_app_number] => 233375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373316 [patent_doc_number] => 06274915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method of improving MOS device performance by controlling degree of depletion in the gate electrode' [patent_app_type] => 1 [patent_app_number] => 9/225646 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2421 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274915.pdf [firstpage_image] =>[orig_patent_app_number] => 225646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1374434 [patent_doc_number] => 06566707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Transistor, semiconductor memory and method of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/223965 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 80 [patent_no_of_words] => 34218 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566707.pdf [firstpage_image] =>[orig_patent_app_number] => 09223965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324524 [patent_doc_number] => 06249013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Microwave-millimeter wave circuit device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/221167 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 8507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249013.pdf [firstpage_image] =>[orig_patent_app_number] => 221167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424752 [patent_doc_number] => 06225678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Layout technique for a matching capacitor array using a continuous top electrode' [patent_app_type] => 1 [patent_app_number] => 9/221634 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3975 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225678.pdf [firstpage_image] =>[orig_patent_app_number] => 221634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4289710 [patent_doc_number] => 06235590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Fabrication of differential gate oxide thicknesses on a single integrated circuit chip' [patent_app_type] => 1 [patent_app_number] => 9/216394 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2951 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235590.pdf [firstpage_image] =>[orig_patent_app_number] => 216394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147551 [patent_doc_number] => 06031246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method of producing semiconductor devices and method of evaluating the same' [patent_app_type] => 1 [patent_app_number] => 9/215625 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5627 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031246.pdf [firstpage_image] =>[orig_patent_app_number] => 215625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422307 [patent_doc_number] => 06194736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Quantum conductive recrystallization barrier layers' [patent_app_type] => 1 [patent_app_number] => 9/213674 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3979 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194736.pdf [firstpage_image] =>[orig_patent_app_number] => 213674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4266073 [patent_doc_number] => 06259150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Voltage dividing resistor and voltage dividing circuit' [patent_app_type] => 1 [patent_app_number] => 9/212244 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2624 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259150.pdf [firstpage_image] =>[orig_patent_app_number] => 212244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4410856 [patent_doc_number] => 06271577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Transistor and method' [patent_app_type] => 1 [patent_app_number] => 9/212136 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2048 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271577.pdf [firstpage_image] =>[orig_patent_app_number] => 212136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1390999 [patent_doc_number] => 06552387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping' [patent_app_type] => B1 [patent_app_number] => 09/211981 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 14836 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552387.pdf [firstpage_image] =>[orig_patent_app_number] => 09211981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1563091 [patent_doc_number] => 06362510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Semiconductor topography having improved active device isolation and reduced dopant migration' [patent_app_type] => B1 [patent_app_number] => 09/206550 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6090 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362510.pdf [firstpage_image] =>[orig_patent_app_number] => 09206550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5885811 [patent_doc_number] => 20020011628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/203098 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15543 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20020011628.pdf [firstpage_image] =>[orig_patent_app_number] => 09203098 [rel_patent_id] =>[rel_patent_doc_number] =>)