Search

Sara W. Crane

Examiner (ID: 10283)

Most Active Art Unit
2811
Art Unit(s)
2503, 2811, 2508, 2899
Total Applications
1624
Issued Applications
1262
Pending Applications
54
Abandoned Applications
308

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4221948 [patent_doc_number] => 06111268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Electronic device' [patent_app_type] => 1 [patent_app_number] => 9/118617 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6429 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111268.pdf [firstpage_image] =>[orig_patent_app_number] => 118617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118617
Electronic device Jul 16, 1998 Issued
Array ( [id] => 4108243 [patent_doc_number] => 06100558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials' [patent_app_type] => 1 [patent_app_number] => 9/116726 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5281 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100558.pdf [firstpage_image] =>[orig_patent_app_number] => 116726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116726
Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials Jul 15, 1998 Issued
Array ( [id] => 4190243 [patent_doc_number] => 06160274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Reduced 1/f low frequency noise high electron mobility transistor' [patent_app_type] => 1 [patent_app_number] => 9/114768 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1966 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160274.pdf [firstpage_image] =>[orig_patent_app_number] => 114768 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114768
Reduced 1/f low frequency noise high electron mobility transistor Jul 13, 1998 Issued
Array ( [id] => 4365876 [patent_doc_number] => 06255675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Programmable capacitor for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/113612 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4662 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255675.pdf [firstpage_image] =>[orig_patent_app_number] => 113612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113612
Programmable capacitor for an integrated circuit Jul 9, 1998 Issued
Array ( [id] => 4410951 [patent_doc_number] => 06271585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Heat sink substrate consisting essentially of copper and molybdenum and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/110669 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13629 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271585.pdf [firstpage_image] =>[orig_patent_app_number] => 110669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110669
Heat sink substrate consisting essentially of copper and molybdenum and method of manufacturing the same Jul 6, 1998 Issued
Array ( [id] => 4113329 [patent_doc_number] => 06057580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Semiconductor memory device having shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/111489 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 49 [patent_no_of_words] => 9645 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057580.pdf [firstpage_image] =>[orig_patent_app_number] => 111489 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111489
Semiconductor memory device having shallow trench isolation structure Jul 6, 1998 Issued
Array ( [id] => 4310387 [patent_doc_number] => 06252293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Laser antifuse using gate capacitor' [patent_app_type] => 1 [patent_app_number] => 9/109605 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2512 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252293.pdf [firstpage_image] =>[orig_patent_app_number] => 109605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109605
Laser antifuse using gate capacitor Jul 1, 1998 Issued
Array ( [id] => 4113247 [patent_doc_number] => 06057575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Scalable flash EEPROM memory cell, method of manufacturing and operation thereof' [patent_app_type] => 1 [patent_app_number] => 9/110096 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 10007 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057575.pdf [firstpage_image] =>[orig_patent_app_number] => 110096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110096
Scalable flash EEPROM memory cell, method of manufacturing and operation thereof Jul 1, 1998 Issued
Array ( [id] => 4309154 [patent_doc_number] => 06188081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Fabrication process and structure of the metal-insulator-semiconductor-insulator-metal (MISIM) multiple-differential-resistance (MNDR) device' [patent_app_type] => 1 [patent_app_number] => 9/108194 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 1464 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188081.pdf [firstpage_image] =>[orig_patent_app_number] => 108194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108194
Fabrication process and structure of the metal-insulator-semiconductor-insulator-metal (MISIM) multiple-differential-resistance (MNDR) device Jun 30, 1998 Issued
Array ( [id] => 4388494 [patent_doc_number] => 06278188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Semiconductor constructions comprising aluminum-containing layers' [patent_app_type] => 1 [patent_app_number] => 9/107929 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1863 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278188.pdf [firstpage_image] =>[orig_patent_app_number] => 107929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107929
Semiconductor constructions comprising aluminum-containing layers Jun 29, 1998 Issued
Array ( [id] => 4343720 [patent_doc_number] => 06284583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/105024 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 8951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284583.pdf [firstpage_image] =>[orig_patent_app_number] => 105024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105024
Semiconductor device and method of manufacturing the same Jun 25, 1998 Issued
Array ( [id] => 6577248 [patent_doc_number] => 20020040988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR THE MANUFACTURE THEREOF' [patent_app_type] => new [patent_app_number] => 09/102616 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 21625 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20020040988.pdf [firstpage_image] =>[orig_patent_app_number] => 09102616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102616
Semiconductor device and method for the manufacture thereof Jun 22, 1998 Issued
Array ( [id] => 4389856 [patent_doc_number] => 06262461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method and apparatus for creating a voltage threshold in a FET' [patent_app_type] => 1 [patent_app_number] => 9/102105 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2515 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262461.pdf [firstpage_image] =>[orig_patent_app_number] => 102105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102105
Method and apparatus for creating a voltage threshold in a FET Jun 21, 1998 Issued
Array ( [id] => 4090698 [patent_doc_number] => 06025624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Shared length cell for improved capacitance' [patent_app_type] => 1 [patent_app_number] => 9/099765 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 3860 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025624.pdf [firstpage_image] =>[orig_patent_app_number] => 099765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099765
Shared length cell for improved capacitance Jun 18, 1998 Issued
Array ( [id] => 4075725 [patent_doc_number] => 06069373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Compact semiconductor device using SOI.cndot.CMOS technology' [patent_app_type] => 1 [patent_app_number] => 9/098864 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4404 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069373.pdf [firstpage_image] =>[orig_patent_app_number] => 098864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098864
Compact semiconductor device using SOI.cndot.CMOS technology Jun 16, 1998 Issued
Array ( [id] => 3940506 [patent_doc_number] => 05929504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor device with trench isolation structure and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/097664 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 7278 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929504.pdf [firstpage_image] =>[orig_patent_app_number] => 097664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097664
Semiconductor device with trench isolation structure and fabrication method thereof Jun 15, 1998 Issued
Array ( [id] => 3947872 [patent_doc_number] => 05982035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'High integrity borderless vias with protective sidewall spacer' [patent_app_type] => 1 [patent_app_number] => 9/094726 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4729 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982035.pdf [firstpage_image] =>[orig_patent_app_number] => 094726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094726
High integrity borderless vias with protective sidewall spacer Jun 14, 1998 Issued
Array ( [id] => 5964561 [patent_doc_number] => 20020089011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'EEPROM CELL WITH A SINGLE POLYSILICON LEVEL AND A SELF-ALGNED TUNNEL AREA' [patent_app_type] => new [patent_app_number] => 09/097435 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2016 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20020089011.pdf [firstpage_image] =>[orig_patent_app_number] => 09097435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097435
EEPROM CELL WITH A SINGLE POLYSILICON LEVEL AND A SELF-ALGNED TUNNEL AREA Jun 14, 1998 Abandoned
Array ( [id] => 4147732 [patent_doc_number] => 06031257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/095745 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031257.pdf [firstpage_image] =>[orig_patent_app_number] => 095745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095745
Semiconductor integrated circuit device Jun 10, 1998 Issued
Array ( [id] => 4264577 [patent_doc_number] => 06204522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Switching device' [patent_app_type] => 1 [patent_app_number] => 9/093725 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4969 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204522.pdf [firstpage_image] =>[orig_patent_app_number] => 093725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093725
Switching device Jun 8, 1998 Issued
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