Search

Sara W. Crane

Examiner (ID: 10283)

Most Active Art Unit
2811
Art Unit(s)
2503, 2811, 2508, 2899
Total Applications
1624
Issued Applications
1262
Pending Applications
54
Abandoned Applications
308

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4364111 [patent_doc_number] => 06191432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Semiconductor device and memory device' [patent_app_type] => 1 [patent_app_number] => 8/921550 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 44 [patent_no_of_words] => 10211 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191432.pdf [firstpage_image] =>[orig_patent_app_number] => 921550 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921550
Semiconductor device and memory device Sep 1, 1997 Issued
Array ( [id] => 3954219 [patent_doc_number] => 05955743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Superconductive tunnel elements, tunnel stacks produced therefrom and use thereof' [patent_app_type] => 1 [patent_app_number] => 8/894912 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10607 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/955/05955743.pdf [firstpage_image] =>[orig_patent_app_number] => 894912 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/894912
Superconductive tunnel elements, tunnel stacks produced therefrom and use thereof Sep 1, 1997 Issued
Array ( [id] => 4013131 [patent_doc_number] => 05889289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'High temperature superconductor/insulator composite thin films with Josephson coupled grains' [patent_app_type] => 1 [patent_app_number] => 8/919346 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5443 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889289.pdf [firstpage_image] =>[orig_patent_app_number] => 919346 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919346
High temperature superconductor/insulator composite thin films with Josephson coupled grains Aug 27, 1997 Issued
Array ( [id] => 3947456 [patent_doc_number] => 05982008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor device using a shallow trench isolation' [patent_app_type] => 1 [patent_app_number] => 8/916428 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5580 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982008.pdf [firstpage_image] =>[orig_patent_app_number] => 916428 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916428
Semiconductor device using a shallow trench isolation Aug 21, 1997 Issued
Array ( [id] => 4162977 [patent_doc_number] => 06114722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Microcrystalline silicon structure and fabrication process' [patent_app_type] => 1 [patent_app_number] => 8/916016 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5389 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114722.pdf [firstpage_image] =>[orig_patent_app_number] => 916016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916016
Microcrystalline silicon structure and fabrication process Aug 20, 1997 Issued
Array ( [id] => 4163542 [patent_doc_number] => 06114762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Atomic wire and atomic wire switch' [patent_app_type] => 1 [patent_app_number] => 8/915730 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3175 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114762.pdf [firstpage_image] =>[orig_patent_app_number] => 915730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915730
Atomic wire and atomic wire switch Aug 20, 1997 Issued
Array ( [id] => 4212304 [patent_doc_number] => 06028336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates, and methods of manufacturing such arrays' [patent_app_type] => 1 [patent_app_number] => 8/908264 [patent_app_country] => US [patent_app_date] => 1997-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3457 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028336.pdf [firstpage_image] =>[orig_patent_app_number] => 908264 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908264
Triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates, and methods of manufacturing such arrays Aug 6, 1997 Issued
Array ( [id] => 3972222 [patent_doc_number] => 05886368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Transistor with silicon oxycarbide gate and methods of fabrication and use' [patent_app_type] => 1 [patent_app_number] => 8/902132 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 8602 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886368.pdf [firstpage_image] =>[orig_patent_app_number] => 902132 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902132
Transistor with silicon oxycarbide gate and methods of fabrication and use Jul 28, 1997 Issued
Array ( [id] => 4019635 [patent_doc_number] => 05880487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/901432 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 12193 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880487.pdf [firstpage_image] =>[orig_patent_app_number] => 901432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901432
Semiconductor device and method for manufacturing the same Jul 24, 1997 Issued
Array ( [id] => 3929181 [patent_doc_number] => 05945700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Semiconductor device having a semiconductor switch structure' [patent_app_type] => 1 [patent_app_number] => 8/899664 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 14613 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945700.pdf [firstpage_image] =>[orig_patent_app_number] => 899664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/899664
Semiconductor device having a semiconductor switch structure Jul 23, 1997 Issued
Array ( [id] => 4049020 [patent_doc_number] => 05909044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Process for forming a high density semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/897176 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4123 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909044.pdf [firstpage_image] =>[orig_patent_app_number] => 897176 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897176
Process for forming a high density semiconductor device Jul 17, 1997 Issued
Array ( [id] => 4091440 [patent_doc_number] => 06018173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Vertically oriented capacitor structure with sloped contact opening and method for etching sloped contact openings in polysilicon' [patent_app_type] => 1 [patent_app_number] => 8/892928 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4111 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018173.pdf [firstpage_image] =>[orig_patent_app_number] => 892928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892928
Vertically oriented capacitor structure with sloped contact opening and method for etching sloped contact openings in polysilicon Jul 14, 1997 Issued
Array ( [id] => 3780145 [patent_doc_number] => 05808335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Reduced mask DRAM process' [patent_app_type] => 1 [patent_app_number] => 8/892334 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4200 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808335.pdf [firstpage_image] =>[orig_patent_app_number] => 892334 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892334
Reduced mask DRAM process Jul 13, 1997 Issued
Array ( [id] => 3782040 [patent_doc_number] => 05818085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Body contact for a MOSFET device fabricated in an SOI layer' [patent_app_type] => 1 [patent_app_number] => 8/892337 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2243 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818085.pdf [firstpage_image] =>[orig_patent_app_number] => 892337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892337
Body contact for a MOSFET device fabricated in an SOI layer Jul 13, 1997 Issued
Array ( [id] => 4189264 [patent_doc_number] => 06150687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Memory cell having a vertical transistor with buried source/drain and dual gates' [patent_app_type] => 1 [patent_app_number] => 8/889462 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7087 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150687.pdf [firstpage_image] =>[orig_patent_app_number] => 889462 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889462
Memory cell having a vertical transistor with buried source/drain and dual gates Jul 7, 1997 Issued
Array ( [id] => 3952456 [patent_doc_number] => 05998804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Transistors incorporating substrates comprising liquid crystal polymers' [patent_app_type] => 1 [patent_app_number] => 8/888022 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4048 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998804.pdf [firstpage_image] =>[orig_patent_app_number] => 888022 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888022
Transistors incorporating substrates comprising liquid crystal polymers Jul 2, 1997 Issued
Array ( [id] => 1009734 [patent_doc_number] => 06900496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-31 [patent_title] => 'Capacitor constructions' [patent_app_type] => utility [patent_app_number] => 08/886388 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 2919 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900496.pdf [firstpage_image] =>[orig_patent_app_number] => 08886388 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886388
Capacitor constructions Jun 30, 1997 Issued
Array ( [id] => 3943553 [patent_doc_number] => 05976932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Memory cell and method for producing the memory cell' [patent_app_type] => 1 [patent_app_number] => 8/884770 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3218 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976932.pdf [firstpage_image] =>[orig_patent_app_number] => 884770 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884770
Memory cell and method for producing the memory cell Jun 29, 1997 Issued
Array ( [id] => 3999146 [patent_doc_number] => 05920103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection' [patent_app_type] => 1 [patent_app_number] => 8/879508 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5488 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920103.pdf [firstpage_image] =>[orig_patent_app_number] => 879508 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879508
Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection Jun 19, 1997 Issued
Array ( [id] => 3947406 [patent_doc_number] => 05982004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Polysilicon devices and a method for fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 8/879886 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4538 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982004.pdf [firstpage_image] =>[orig_patent_app_number] => 879886 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879886
Polysilicon devices and a method for fabrication thereof Jun 19, 1997 Issued
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