
Sarai E. Butler
Examiner (ID: 6911, Phone: (571)270-3823 , Office: P/2114 )
| Most Active Art Unit | 2114 |
| Art Unit(s) | 2114 |
| Total Applications | 1400 |
| Issued Applications | 1216 |
| Pending Applications | 71 |
| Abandoned Applications | 137 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19573823
[patent_doc_number] => 20240378115
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-14
[patent_title] => MEMORY SYSTEMS AND OPERATING METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/781592
[patent_app_country] => US
[patent_app_date] => 2024-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10813
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781592
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/781592 | Memory systems and operating methods thereof | Jul 22, 2024 | Issued |
Array
(
[id] => 20609940
[patent_doc_number] => 12585542
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-24
[patent_title] => Locked raid with compression for memory interconnect applications having a shared cache line
[patent_app_type] => utility
[patent_app_number] => 18/778641
[patent_app_country] => US
[patent_app_date] => 2024-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 12666
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778641
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/778641 | Locked raid with compression for memory interconnect applications having a shared cache line | Jul 18, 2024 | Issued |
Array
(
[id] => 19545123
[patent_doc_number] => 20240362159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => Testing a metaverse application for rendering errors across multiple devices
[patent_app_type] => utility
[patent_app_number] => 18/769134
[patent_app_country] => US
[patent_app_date] => 2024-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19661
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769134
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/769134 | Testing a metaverse application for rendering errors across multiple devices | Jul 9, 2024 | Issued |
Array
(
[id] => 19819146
[patent_doc_number] => 20250077353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 18/762284
[patent_app_country] => US
[patent_app_date] => 2024-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26940
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762284
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/762284 | DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES | Jul 1, 2024 | Pending |
Array
(
[id] => 19819146
[patent_doc_number] => 20250077353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 18/762284
[patent_app_country] => US
[patent_app_date] => 2024-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26940
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762284
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/762284 | DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES | Jul 1, 2024 | Pending |
Array
(
[id] => 20446991
[patent_doc_number] => 20260003713
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-01
[patent_title] => HOST-FACING DMA FAILURE DETECTION FOR TRANSPORT OFFLOAD WITH MULTI-STAGE QUEUE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/758279
[patent_app_country] => US
[patent_app_date] => 2024-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1149
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758279
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/758279 | HOST-FACING DMA FAILURE DETECTION FOR TRANSPORT OFFLOAD WITH MULTI-STAGE QUEUE OPERATIONS | Jun 27, 2024 | Pending |
Array
(
[id] => 20428314
[patent_doc_number] => 20250390406
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-25
[patent_title] => METHOD AND SYSTEM FOR AUTOMATIC VALIDATION OF DATA DELIVERY
[patent_app_type] => utility
[patent_app_number] => 18/750660
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2110
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750660
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/750660 | METHOD AND SYSTEM FOR AUTOMATIC VALIDATION OF DATA DELIVERY | Jun 20, 2024 | Pending |
Array
(
[id] => 19499287
[patent_doc_number] => 20240338305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => Systems and Methods for Connection Switch Automation
[patent_app_type] => utility
[patent_app_number] => 18/746723
[patent_app_country] => US
[patent_app_date] => 2024-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4019
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746723
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/746723 | Systems and methods for connection switch automation | Jun 17, 2024 | Issued |
Array
(
[id] => 19482071
[patent_doc_number] => 20240330113
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => Meta Data Protection against Unexpected Power Loss in a Memory System
[patent_app_type] => utility
[patent_app_number] => 18/743343
[patent_app_country] => US
[patent_app_date] => 2024-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6568
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743343
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/743343 | Meta Data Protection against Unexpected Power Loss in a Memory System | Jun 13, 2024 | Pending |
Array
(
[id] => 20415714
[patent_doc_number] => 12499000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-16
[patent_title] => Functional metadata system and method for data quality inspection
[patent_app_type] => utility
[patent_app_number] => 18/733861
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 0
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733861
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/733861 | Functional metadata system and method for data quality inspection | Jun 4, 2024 | Issued |
Array
(
[id] => 19434662
[patent_doc_number] => 20240303160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => Preference Based Selection of Storage Network Memory for Data Storage
[patent_app_type] => utility
[patent_app_number] => 18/665616
[patent_app_country] => US
[patent_app_date] => 2024-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 34963
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665616
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/665616 | Preference based selection of storage network memory for data storage | May 15, 2024 | Issued |
Array
(
[id] => 20537488
[patent_doc_number] => 12554565
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-17
[patent_title] => Information processing device, information processing method, and computer program product
[patent_app_type] => utility
[patent_app_number] => 18/664411
[patent_app_country] => US
[patent_app_date] => 2024-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4845
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664411
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/664411 | Information processing device, information processing method, and computer program product | May 14, 2024 | Issued |
Array
(
[id] => 20323191
[patent_doc_number] => 20250335279
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-30
[patent_title] => SMART CASE SCENARIO DESIGN MECHANISM FOR REPRODUCING CUSTOMER ISSUES
[patent_app_type] => utility
[patent_app_number] => 18/660307
[patent_app_country] => US
[patent_app_date] => 2024-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2316
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660307
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/660307 | Smart case scenario design mechanism for reproducing customer issues | May 9, 2024 | Issued |
Array
(
[id] => 20317232
[patent_doc_number] => 12455783
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-28
[patent_title] => Infrastructure for preventing compromise of operating system kernels due to discovered errors
[patent_app_type] => utility
[patent_app_number] => 18/658565
[patent_app_country] => US
[patent_app_date] => 2024-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 3459
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658565
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/658565 | Infrastructure for preventing compromise of operating system kernels due to discovered errors | May 7, 2024 | Issued |
Array
(
[id] => 20344879
[patent_doc_number] => 12468611
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Unified fault and stability analysis system and method considering unbalanced topologies
[patent_app_type] => utility
[patent_app_number] => 18/654042
[patent_app_country] => US
[patent_app_date] => 2024-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1026
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654042
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/654042 | Unified fault and stability analysis system and method considering unbalanced topologies | May 2, 2024 | Issued |
Array
(
[id] => 20087291
[patent_doc_number] => 20250217227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => XML INTERPRETER
[patent_app_type] => utility
[patent_app_number] => 18/655037
[patent_app_country] => US
[patent_app_date] => 2024-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8893
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655037
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/655037 | XML interpreter | May 2, 2024 | Issued |
Array
(
[id] => 20323209
[patent_doc_number] => 20250335297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-30
[patent_title] => INTELLIGENTLY FORMING DATA STRIPES INCLUDING MULTIPLE SHARDS IN A SINGLE FAILURE DOMAIN
[patent_app_type] => utility
[patent_app_number] => 18/651149
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33580
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651149
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651149 | Intelligently forming data stripes including multiple shards in a single failure domain | Apr 29, 2024 | Issued |
Array
(
[id] => 20323232
[patent_doc_number] => 20250335320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-30
[patent_title] => DETERMINING HARDWARE ISSUES AND RECOMMENDING CORRESPONDING ACTIONS USING ARTIFICIAL INTELLIGENCE TECHNIQUES
[patent_app_type] => utility
[patent_app_number] => 18/647531
[patent_app_country] => US
[patent_app_date] => 2024-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3460
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647531
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/647531 | Determining hardware issues and recommending corresponding actions using artificial intelligence techniques | Apr 25, 2024 | Issued |
Array
(
[id] => 20110176
[patent_doc_number] => 12360897
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Systems and methods to flush data in persistent memory region to non-volatile memory using auxiliary processor
[patent_app_type] => utility
[patent_app_number] => 18/635949
[patent_app_country] => US
[patent_app_date] => 2024-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5418
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635949
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/635949 | Systems and methods to flush data in persistent memory region to non-volatile memory using auxiliary processor | Apr 14, 2024 | Issued |
Array
(
[id] => 19949866
[patent_doc_number] => 12321228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Selectable signal, logging, and state extraction
[patent_app_type] => utility
[patent_app_number] => 18/627278
[patent_app_country] => US
[patent_app_date] => 2024-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7337
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627278
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/627278 | Selectable signal, logging, and state extraction | Apr 3, 2024 | Issued |