
Sarira Camilla Pourbohloul
Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )
| Most Active Art Unit | 1765 |
| Art Unit(s) | 1765, 1796 |
| Total Applications | 236 |
| Issued Applications | 141 |
| Pending Applications | 1 |
| Abandoned Applications | 95 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1192484
[patent_doc_number] => 06735682
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-11
[patent_title] => 'Apparatus and method for address calculation'
[patent_app_type] => B2
[patent_app_number] => 10/112254
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3071
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/735/06735682.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112254
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112254 | Apparatus and method for address calculation | Mar 27, 2002 | Issued |
Array
(
[id] => 6731917
[patent_doc_number] => 20030188107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'External bus transaction scheduling system'
[patent_app_type] => new
[patent_app_number] => 10/113546
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7816
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20030188107.pdf
[firstpage_image] =>[orig_patent_app_number] => 10113546
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/113546 | External bus transaction scheduling system | Mar 27, 2002 | Issued |
Array
(
[id] => 6798255
[patent_doc_number] => 20030177130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-18
[patent_title] => 'Method, system, program, and data structures for maintaining metadata in a storage system'
[patent_app_type] => new
[patent_app_number] => 10/096400
[patent_app_country] => US
[patent_app_date] => 2002-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7597
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20030177130.pdf
[firstpage_image] =>[orig_patent_app_number] => 10096400
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/096400 | Method, system, program, and data structures for maintaining metadata in a storage system | Mar 11, 2002 | Issued |
Array
(
[id] => 1339347
[patent_doc_number] => 06601154
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-29
[patent_title] => 'Cache memory employing dynamically controlled data array start timing and a microcomputer using the same'
[patent_app_type] => B2
[patent_app_number] => 10/084229
[patent_app_country] => US
[patent_app_date] => 2002-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8332
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/601/06601154.pdf
[firstpage_image] =>[orig_patent_app_number] => 10084229
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/084229 | Cache memory employing dynamically controlled data array start timing and a microcomputer using the same | Feb 27, 2002 | Issued |
Array
(
[id] => 1411423
[patent_doc_number] => 06553452
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-04-22
[patent_title] => 'Synchronous memory device having a temperature register'
[patent_app_type] => B2
[patent_app_number] => 10/051957
[patent_app_country] => US
[patent_app_date] => 2002-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3904
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/553/06553452.pdf
[firstpage_image] =>[orig_patent_app_number] => 10051957
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/051957 | Synchronous memory device having a temperature register | Jan 17, 2002 | Issued |
Array
(
[id] => 1243152
[patent_doc_number] => 06684317
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-27
[patent_title] => 'Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor'
[patent_app_type] => B2
[patent_app_number] => 10/026166
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3385
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/684/06684317.pdf
[firstpage_image] =>[orig_patent_app_number] => 10026166
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/026166 | Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor | Dec 20, 2001 | Issued |
Array
(
[id] => 1177494
[patent_doc_number] => 06760810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-06
[patent_title] => 'Data processor having instruction cache with low power consumption'
[patent_app_type] => B2
[patent_app_number] => 10/023905
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3915
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/760/06760810.pdf
[firstpage_image] =>[orig_patent_app_number] => 10023905
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/023905 | Data processor having instruction cache with low power consumption | Dec 20, 2001 | Issued |
Array
(
[id] => 6685008
[patent_doc_number] => 20030120872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'System, method, and article of manufacture for dynamically profiling memory transfers in a program'
[patent_app_type] => new
[patent_app_number] => 10/026313
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 22442
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20030120872.pdf
[firstpage_image] =>[orig_patent_app_number] => 10026313
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/026313 | System, method, and article of manufacture for dynamically profiling memory transfers in a program | Dec 20, 2001 | Issued |
Array
(
[id] => 6685014
[patent_doc_number] => 20030120878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Resource sharing using a locking mechanism in a multiprocessor environment'
[patent_app_type] => new
[patent_app_number] => 10/024038
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2145
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20030120878.pdf
[firstpage_image] =>[orig_patent_app_number] => 10024038
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/024038 | Resource sharing using a locking mechanism in a multiprocessor environment | Dec 20, 2001 | Abandoned |
Array
(
[id] => 6685022
[patent_doc_number] => 20030120886
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Method and apparatus for buffer partitioning without loss of data'
[patent_app_type] => new
[patent_app_number] => 10/037163
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5043
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20030120886.pdf
[firstpage_image] =>[orig_patent_app_number] => 10037163
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/037163 | Method and apparatus for buffer partitioning without loss of data | Dec 20, 2001 | Issued |
Array
(
[id] => 6685003
[patent_doc_number] => 20030120867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Context-sensitive caching'
[patent_app_type] => new
[patent_app_number] => 10/026388
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2933
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20030120867.pdf
[firstpage_image] =>[orig_patent_app_number] => 10026388
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/026388 | Context-sensitive caching | Dec 20, 2001 | Issued |
Array
(
[id] => 5848399
[patent_doc_number] => 20020133683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-19
[patent_title] => 'Method and system for reducing fragmentation'
[patent_app_type] => new
[patent_app_number] => 10/028123
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2338
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20020133683.pdf
[firstpage_image] =>[orig_patent_app_number] => 10028123
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/028123 | Method and system for reducing fragmentation | Dec 20, 2001 | Issued |
Array
(
[id] => 6685025
[patent_doc_number] => 20030120889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Unaligned memory operands'
[patent_app_type] => new
[patent_app_number] => 10/029367
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3411
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20030120889.pdf
[firstpage_image] =>[orig_patent_app_number] => 10029367
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/029367 | Unaligned memory operands | Dec 20, 2001 | Issued |
Array
(
[id] => 6685015
[patent_doc_number] => 20030120879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Methods and apparatus for forming linked list queue using chunk-based structure'
[patent_app_type] => new
[patent_app_number] => 10/029680
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3438
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20030120879.pdf
[firstpage_image] =>[orig_patent_app_number] => 10029680
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/029680 | Methods and apparatus for forming linked list queue using chunk-based structure | Dec 20, 2001 | Issued |
Array
(
[id] => 1083001
[patent_doc_number] => 06836832
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-28
[patent_title] => 'System and method for pre-selecting candidate disks based on validity for volume'
[patent_app_type] => B1
[patent_app_number] => 10/027909
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 6778
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/836/06836832.pdf
[firstpage_image] =>[orig_patent_app_number] => 10027909
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/027909 | System and method for pre-selecting candidate disks based on validity for volume | Dec 20, 2001 | Issued |
Array
(
[id] => 7633096
[patent_doc_number] => 06658524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Memory with call out function'
[patent_app_type] => B1
[patent_app_number] => 09/914918
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6144
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/658/06658524.pdf
[firstpage_image] =>[orig_patent_app_number] => 09914918
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/914918 | Memory with call out function | Dec 20, 2001 | Issued |
Array
(
[id] => 1138941
[patent_doc_number] => 06789163
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-07
[patent_title] => 'Optimizing data transfer performance through partial write command purging in a disc drive'
[patent_app_type] => B2
[patent_app_number] => 10/029459
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 5932
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/789/06789163.pdf
[firstpage_image] =>[orig_patent_app_number] => 10029459
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/029459 | Optimizing data transfer performance through partial write command purging in a disc drive | Dec 20, 2001 | Issued |
Array
(
[id] => 6722363
[patent_doc_number] => 20030056053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-20
[patent_title] => 'Low power semiconductor memory device having a normal mode and a partial array self refresh mode'
[patent_app_type] => new
[patent_app_number] => 10/024366
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3046
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20030056053.pdf
[firstpage_image] =>[orig_patent_app_number] => 10024366
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/024366 | Low power semiconductor memory device having a normal mode and a partial array self refresh mode | Dec 20, 2001 | Issued |
Array
(
[id] => 6685004
[patent_doc_number] => 20030120868
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Method and system to cache metadata'
[patent_app_type] => new
[patent_app_number] => 10/026398
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2573
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20030120868.pdf
[firstpage_image] =>[orig_patent_app_number] => 10026398
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/026398 | Method and system to cache metadata | Dec 20, 2001 | Issued |
Array
(
[id] => 6685020
[patent_doc_number] => 20030120884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Memory system for increased bandwidth'
[patent_app_type] => new
[patent_app_number] => 10/026350
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2226
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20030120884.pdf
[firstpage_image] =>[orig_patent_app_number] => 10026350
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/026350 | Memory system for increased bandwidth | Dec 20, 2001 | Issued |