Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1557582 [patent_doc_number] => 06401187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Memory access optimizing method' [patent_app_type] => B1 [patent_app_number] => 09/581361 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 13136 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401187.pdf [firstpage_image] =>[orig_patent_app_number] => 09581361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/581361
Memory access optimizing method Jun 11, 2000 Issued
Array ( [id] => 7080119 [patent_doc_number] => 20010042182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Asynchronous request/synchronous data dynamic random access memory' [patent_app_type] => new [patent_app_number] => 09/583111 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10146 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042182.pdf [firstpage_image] =>[orig_patent_app_number] => 09583111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583111
Memory device having an internal register May 22, 2000 Issued
Array ( [id] => 1308846 [patent_doc_number] => 06629213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Apparatus and method using sub-cacheline transactions to improve system performance' [patent_app_type] => B1 [patent_app_number] => 09/561689 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5133 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629213.pdf [firstpage_image] =>[orig_patent_app_number] => 09561689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561689
Apparatus and method using sub-cacheline transactions to improve system performance Apr 30, 2000 Issued
Array ( [id] => 4346473 [patent_doc_number] => 06330651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Information processing apparatus capable of reading data from memory at high speed' [patent_app_type] => 1 [patent_app_number] => 9/563754 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6292 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330651.pdf [firstpage_image] =>[orig_patent_app_number] => 563754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/563754
Information processing apparatus capable of reading data from memory at high speed Apr 30, 2000 Issued
Array ( [id] => 4423765 [patent_doc_number] => 06240499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method and system for improving data storage and access for programs written in mid-level programming languages' [patent_app_type] => 1 [patent_app_number] => 9/559683 [patent_app_country] => US [patent_app_date] => 2000-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6913 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240499.pdf [firstpage_image] =>[orig_patent_app_number] => 559683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559683
Method and system for improving data storage and access for programs written in mid-level programming languages Apr 26, 2000 Issued
Array ( [id] => 1481132 [patent_doc_number] => 06389523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Cache memory employing dynamically controlled data array start timing and a microprocessor using the same' [patent_app_type] => B1 [patent_app_number] => 09/557220 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8312 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389523.pdf [firstpage_image] =>[orig_patent_app_number] => 09557220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/557220
Cache memory employing dynamically controlled data array start timing and a microprocessor using the same Apr 24, 2000 Issued
Array ( [id] => 1431230 [patent_doc_number] => 06523102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'PARALLEL COMPRESSION/DECOMPRESSION SYSTEM AND METHOD FOR IMPLEMENTATION OF IN-MEMORY COMPRESSED CACHE IMPROVING STORAGE DENSITY AND ACCESS SPEED FOR INDUSTRY STANDARD MEMORY SUBSYSTEMS AND IN-LINE MEMORY MODULES' [patent_app_type] => B1 [patent_app_number] => 09/550380 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 92 [patent_no_of_words] => 51606 [patent_no_of_claims] => 143 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523102.pdf [firstpage_image] =>[orig_patent_app_number] => 09550380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/550380
PARALLEL COMPRESSION/DECOMPRESSION SYSTEM AND METHOD FOR IMPLEMENTATION OF IN-MEMORY COMPRESSED CACHE IMPROVING STORAGE DENSITY AND ACCESS SPEED FOR INDUSTRY STANDARD MEMORY SUBSYSTEMS AND IN-LINE MEMORY MODULES Apr 13, 2000 Issued
Array ( [id] => 4381355 [patent_doc_number] => 06256717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Data access controller and data access control method' [patent_app_type] => 1 [patent_app_number] => 9/539765 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4440 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256717.pdf [firstpage_image] =>[orig_patent_app_number] => 539765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539765
Data access controller and data access control method Mar 30, 2000 Issued
Array ( [id] => 7642384 [patent_doc_number] => 06430662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and device for changing memory contents in a control unit, especially of a motor vehicle' [patent_app_type] => B1 [patent_app_number] => 09/383309 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5916 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430662.pdf [firstpage_image] =>[orig_patent_app_number] => 09383309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383309
Method and device for changing memory contents in a control unit, especially of a motor vehicle Feb 13, 2000 Issued
Array ( [id] => 1513297 [patent_doc_number] => 06442666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Techniques for improving memory access in a virtual memory system' [patent_app_type] => B1 [patent_app_number] => 09/491408 [patent_app_country] => US [patent_app_date] => 2000-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5438 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442666.pdf [firstpage_image] =>[orig_patent_app_number] => 09491408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491408
Techniques for improving memory access in a virtual memory system Jan 25, 2000 Issued
Array ( [id] => 1289190 [patent_doc_number] => 06647479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Computer file system providing looped file structure for post-occurrence data collection of asynchronous events' [patent_app_type] => B1 [patent_app_number] => 09/476701 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5690 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647479.pdf [firstpage_image] =>[orig_patent_app_number] => 09476701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476701
Computer file system providing looped file structure for post-occurrence data collection of asynchronous events Jan 2, 2000 Issued
Array ( [id] => 1595887 [patent_doc_number] => 06484239 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Prefetch queue' [patent_app_type] => B1 [patent_app_number] => 09/474012 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4322 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484239.pdf [firstpage_image] =>[orig_patent_app_number] => 09474012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474012
Prefetch queue Dec 27, 1999 Issued
Array ( [id] => 6717355 [patent_doc_number] => 20030028703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'DISK ARRAY DEVICE CAPABLE OF PROVIDING LOGICAL DISKS FOR EACH HOST COMPUTER REGARDLESS OF LIMITATION OF THE OTHER HOST COMPUTERS' [patent_app_type] => new [patent_app_number] => 09/464412 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2208 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028703.pdf [firstpage_image] =>[orig_patent_app_number] => 09464412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464412
DISK ARRAY DEVICE CAPABLE OF PROVIDING LOGICAL DISKS FOR EACH HOST COMPUTER REGARDLESS OF LIMITATION OF THE OTHER HOST COMPUTERS Dec 15, 1999 Abandoned
Array ( [id] => 1539176 [patent_doc_number] => 06412049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method for minimizing CPU memory latency while transferring streaming data' [patent_app_type] => B1 [patent_app_number] => 09/465528 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5904 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412049.pdf [firstpage_image] =>[orig_patent_app_number] => 09465528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465528
Method for minimizing CPU memory latency while transferring streaming data Dec 15, 1999 Issued
Array ( [id] => 1524905 [patent_doc_number] => 06415367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme' [patent_app_type] => B1 [patent_app_number] => 09/465527 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5990 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415367.pdf [firstpage_image] =>[orig_patent_app_number] => 09465527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465527
Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme Dec 15, 1999 Issued
Array ( [id] => 1429761 [patent_doc_number] => 06510491 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'System and method for accomplishing data storage migration between raid levels' [patent_app_type] => B1 [patent_app_number] => 09/465057 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3873 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510491.pdf [firstpage_image] =>[orig_patent_app_number] => 09465057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465057
System and method for accomplishing data storage migration between raid levels Dec 15, 1999 Issued
Array ( [id] => 1567442 [patent_doc_number] => 06363461 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Apparatus for memory resource arbitration based on dedicated time slot allocation' [patent_app_type] => B1 [patent_app_number] => 09/465537 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5978 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363461.pdf [firstpage_image] =>[orig_patent_app_number] => 09465537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465537
Apparatus for memory resource arbitration based on dedicated time slot allocation Dec 15, 1999 Issued
Array ( [id] => 1434051 [patent_doc_number] => 06341341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'System and method for disk control with snapshot feature including read-write snapshot half' [patent_app_type] => B1 [patent_app_number] => 09/465354 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4287 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341341.pdf [firstpage_image] =>[orig_patent_app_number] => 09465354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465354
System and method for disk control with snapshot feature including read-write snapshot half Dec 15, 1999 Issued
Array ( [id] => 1339277 [patent_doc_number] => 06601149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Memory transaction monitoring system and user interface' [patent_app_type] => B1 [patent_app_number] => 09/460831 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6316 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601149.pdf [firstpage_image] =>[orig_patent_app_number] => 09460831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460831
Memory transaction monitoring system and user interface Dec 13, 1999 Issued
Array ( [id] => 1431082 [patent_doc_number] => 06507899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Interface for a memory unit' [patent_app_type] => B1 [patent_app_number] => 09/460534 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5141 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507899.pdf [firstpage_image] =>[orig_patent_app_number] => 09460534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460534
Interface for a memory unit Dec 12, 1999 Issued
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