Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4388199 [patent_doc_number] => 06275906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Coherency maintenance in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 9/315487 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10197 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275906.pdf [firstpage_image] =>[orig_patent_app_number] => 315487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315487
Coherency maintenance in a multiprocessor system May 19, 1999 Issued
Array ( [id] => 1540074 [patent_doc_number] => 06338121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Data source arbitration in a multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/315539 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10431 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338121.pdf [firstpage_image] =>[orig_patent_app_number] => 09315539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315539
Data source arbitration in a multiprocessor system May 19, 1999 Issued
Array ( [id] => 4422470 [patent_doc_number] => 06272601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Critical word forwarding in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 9/315541 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272601.pdf [firstpage_image] =>[orig_patent_app_number] => 315541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315541
Critical word forwarding in a multiprocessor system May 19, 1999 Issued
Array ( [id] => 7642388 [patent_doc_number] => 06430658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Local cache-to-cache transfers in a multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/315540 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430658.pdf [firstpage_image] =>[orig_patent_app_number] => 09315540 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315540
Local cache-to-cache transfers in a multiprocessor system May 19, 1999 Issued
Array ( [id] => 4290270 [patent_doc_number] => 06308245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Adaptive, time-based synchronization mechanism for an integrated posix file system' [patent_app_type] => 1 [patent_app_number] => 9/311136 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6405 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308245.pdf [firstpage_image] =>[orig_patent_app_number] => 311136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311136
Adaptive, time-based synchronization mechanism for an integrated posix file system May 12, 1999 Issued
Array ( [id] => 4400249 [patent_doc_number] => 06304945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method and apparatus for maintaining cache coherency in a computer system having multiple processor buses' [patent_app_type] => 1 [patent_app_number] => 9/311082 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3732 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304945.pdf [firstpage_image] =>[orig_patent_app_number] => 311082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311082
Method and apparatus for maintaining cache coherency in a computer system having multiple processor buses May 12, 1999 Issued
Array ( [id] => 1443898 [patent_doc_number] => 06336164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method and system for preventing deadlock in a log structured array' [patent_app_type] => B1 [patent_app_number] => 09/311205 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3722 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336164.pdf [firstpage_image] =>[orig_patent_app_number] => 09311205 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311205
Method and system for preventing deadlock in a log structured array May 11, 1999 Issued
Array ( [id] => 4366333 [patent_doc_number] => 06286092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Paged based memory address translation table update method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/310564 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3876 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286092.pdf [firstpage_image] =>[orig_patent_app_number] => 310564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310564
Paged based memory address translation table update method and apparatus May 11, 1999 Issued
Array ( [id] => 4270185 [patent_doc_number] => 06223257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Instruction cache address generation technique having reduced delays in fetching missed data' [patent_app_type] => 1 [patent_app_number] => 9/310659 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5697 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223257.pdf [firstpage_image] =>[orig_patent_app_number] => 310659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310659
Instruction cache address generation technique having reduced delays in fetching missed data May 11, 1999 Issued
Array ( [id] => 1377227 [patent_doc_number] => 06578131 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Scaleable hash table for shared-memory multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/300715 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8222 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578131.pdf [firstpage_image] =>[orig_patent_app_number] => 09300715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300715
Scaleable hash table for shared-memory multiprocessor system Apr 26, 1999 Issued
Array ( [id] => 4199820 [patent_doc_number] => 06021461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method for reducing power consumption in a set associative cache memory system' [patent_app_type] => 1 [patent_app_number] => 9/244079 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3067 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021461.pdf [firstpage_image] =>[orig_patent_app_number] => 244079 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244079
Method for reducing power consumption in a set associative cache memory system Feb 3, 1999 Issued
Array ( [id] => 4424552 [patent_doc_number] => 06266750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Variable length pipeline with parallel functional units' [patent_app_type] => 1 [patent_app_number] => 9/232051 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7439 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266750.pdf [firstpage_image] =>[orig_patent_app_number] => 232051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232051
Variable length pipeline with parallel functional units Jan 14, 1999 Issued
Array ( [id] => 4399308 [patent_doc_number] => 06295588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Memory access controller that converts memory access requests into memory access commands' [patent_app_type] => 1 [patent_app_number] => 9/231019 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4548 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295588.pdf [firstpage_image] =>[orig_patent_app_number] => 231019 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231019
Memory access controller that converts memory access requests into memory access commands Jan 13, 1999 Issued
Array ( [id] => 4423717 [patent_doc_number] => 06240494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Subsystem replacement method' [patent_app_type] => 1 [patent_app_number] => 9/212410 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8024 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240494.pdf [firstpage_image] =>[orig_patent_app_number] => 212410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212410
Subsystem replacement method Dec 15, 1998 Issued
Array ( [id] => 4427297 [patent_doc_number] => 06226720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method for optimally configuring memory in a mixed interleave system' [patent_app_type] => 1 [patent_app_number] => 9/210505 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4601 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226720.pdf [firstpage_image] =>[orig_patent_app_number] => 210505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210505
Method for optimally configuring memory in a mixed interleave system Dec 10, 1998 Issued
Array ( [id] => 4381341 [patent_doc_number] => 06256716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Apparatus, system and method for reducing bus contention during consecutive read-write operations' [patent_app_type] => 1 [patent_app_number] => 9/209974 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6301 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256716.pdf [firstpage_image] =>[orig_patent_app_number] => 209974 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209974
Apparatus, system and method for reducing bus contention during consecutive read-write operations Dec 9, 1998 Issued
Array ( [id] => 4427298 [patent_doc_number] => 06226721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method and system for generating and utilizing speculative memory access requests in data processing systems' [patent_app_type] => 1 [patent_app_number] => 9/208569 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 39 [patent_no_of_words] => 9862 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226721.pdf [firstpage_image] =>[orig_patent_app_number] => 208569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208569
Method and system for generating and utilizing speculative memory access requests in data processing systems Dec 8, 1998 Issued
Array ( [id] => 4376705 [patent_doc_number] => 06219769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and system for origin-sensitive memory control and access in data processing systems' [patent_app_type] => 1 [patent_app_number] => 9/208305 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 37 [patent_no_of_words] => 9811 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219769.pdf [firstpage_image] =>[orig_patent_app_number] => 208305 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208305
Method and system for origin-sensitive memory control and access in data processing systems Dec 8, 1998 Issued
Array ( [id] => 4388141 [patent_doc_number] => 06275902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Data processor with variable types of cache memories and a controller for selecting a cache memory to be access' [patent_app_type] => 1 [patent_app_number] => 9/188693 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 55 [patent_no_of_words] => 24029 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275902.pdf [firstpage_image] =>[orig_patent_app_number] => 188693 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188693
Data processor with variable types of cache memories and a controller for selecting a cache memory to be access Nov 9, 1998 Issued
Array ( [id] => 4252417 [patent_doc_number] => 06076140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Set associative cache memory system with reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 9/187340 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3068 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076140.pdf [firstpage_image] =>[orig_patent_app_number] => 187340 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187340
Set associative cache memory system with reduced power consumption Nov 5, 1998 Issued
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