Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4427303 [patent_doc_number] => 06226726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Memory bank organization correlating distance with a memory map' [patent_app_type] => 1 [patent_app_number] => 9/075946 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4666 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226726.pdf [firstpage_image] =>[orig_patent_app_number] => 075946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075946
Memory bank organization correlating distance with a memory map May 11, 1998 Issued
Array ( [id] => 4337220 [patent_doc_number] => 06249852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method for heap management of fixed sized objects using pages' [patent_app_type] => 1 [patent_app_number] => 9/075016 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4581 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249852.pdf [firstpage_image] =>[orig_patent_app_number] => 075016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075016
Method for heap management of fixed sized objects using pages May 7, 1998 Issued
Array ( [id] => 4427296 [patent_doc_number] => 06226719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Organizing memory extents of OS input/output control' [patent_app_type] => 1 [patent_app_number] => 9/075408 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5459 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226719.pdf [firstpage_image] =>[orig_patent_app_number] => 075408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075408
Organizing memory extents of OS input/output control May 7, 1998 Issued
Array ( [id] => 4424582 [patent_doc_number] => 06266757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'High speed four-to-two carry save adder' [patent_app_type] => 1 [patent_app_number] => 9/074019 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3395 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266757.pdf [firstpage_image] =>[orig_patent_app_number] => 074019 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074019
High speed four-to-two carry save adder May 5, 1998 Issued
Array ( [id] => 4270032 [patent_doc_number] => 06223248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access' [patent_app_type] => 1 [patent_app_number] => 9/067575 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 36471 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223248.pdf [firstpage_image] =>[orig_patent_app_number] => 067575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067575
Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access Apr 27, 1998 Issued
Array ( [id] => 4422243 [patent_doc_number] => 06233661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Computer system with memory controller that hides the next cycle during the current cycle' [patent_app_type] => 1 [patent_app_number] => 9/069458 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9054 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233661.pdf [firstpage_image] =>[orig_patent_app_number] => 069458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069458
Computer system with memory controller that hides the next cycle during the current cycle Apr 27, 1998 Issued
Array ( [id] => 4376393 [patent_doc_number] => 06219751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Device level coordination of access operations among multiple raid control units' [patent_app_type] => 1 [patent_app_number] => 9/069070 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5622 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219751.pdf [firstpage_image] =>[orig_patent_app_number] => 069070 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069070
Device level coordination of access operations among multiple raid control units Apr 27, 1998 Issued
Array ( [id] => 4209007 [patent_doc_number] => 06154823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method of recognizing fixed and variable sized data objects in memory' [patent_app_type] => 1 [patent_app_number] => 9/067578 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4565 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154823.pdf [firstpage_image] =>[orig_patent_app_number] => 067578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067578
Method of recognizing fixed and variable sized data objects in memory Apr 27, 1998 Issued
Array ( [id] => 4404014 [patent_doc_number] => 06263413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Memory integrated circuit and main memory and graphics memory systems applying the above' [patent_app_type] => 1 [patent_app_number] => 9/066605 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 9716 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263413.pdf [firstpage_image] =>[orig_patent_app_number] => 066605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066605
Memory integrated circuit and main memory and graphics memory systems applying the above Apr 26, 1998 Issued
Array ( [id] => 4273668 [patent_doc_number] => 06209073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'System and method for interlocking barrier operations in load and store queues' [patent_app_type] => 1 [patent_app_number] => 9/066961 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3323 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209073.pdf [firstpage_image] =>[orig_patent_app_number] => 066961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066961
System and method for interlocking barrier operations in load and store queues Apr 26, 1998 Issued
Array ( [id] => 4346484 [patent_doc_number] => 06330652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method and apparatus for high-speed data queuing and data retrieval' [patent_app_type] => 1 [patent_app_number] => 9/063866 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3539 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330652.pdf [firstpage_image] =>[orig_patent_app_number] => 063866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063866
Method and apparatus for high-speed data queuing and data retrieval Apr 21, 1998 Issued
Array ( [id] => 4208996 [patent_doc_number] => 06154822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method and system for improving data storage and access for programs written in mid-level programming languages' [patent_app_type] => 1 [patent_app_number] => 9/063683 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6913 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154822.pdf [firstpage_image] =>[orig_patent_app_number] => 063683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063683
Method and system for improving data storage and access for programs written in mid-level programming languages Apr 20, 1998 Issued
Array ( [id] => 4152376 [patent_doc_number] => 06148363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Device and method for controlling solid-state memory system' [patent_app_type] => 1 [patent_app_number] => 9/064528 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 8504 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148363.pdf [firstpage_image] =>[orig_patent_app_number] => 064528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064528
Device and method for controlling solid-state memory system Apr 20, 1998 Issued
Array ( [id] => 4122069 [patent_doc_number] => 06052765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method for optimized placement of virtual volumes on a physical cartridge' [patent_app_type] => 1 [patent_app_number] => 9/063986 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1199 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052765.pdf [firstpage_image] =>[orig_patent_app_number] => 063986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063986
Method for optimized placement of virtual volumes on a physical cartridge Apr 20, 1998 Issued
Array ( [id] => 4427302 [patent_doc_number] => 06226725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method and system in a data processing system for the dedication of memory storage locations' [patent_app_type] => 1 [patent_app_number] => 9/063913 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2867 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226725.pdf [firstpage_image] =>[orig_patent_app_number] => 063913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063913
Method and system in a data processing system for the dedication of memory storage locations Apr 20, 1998 Issued
Array ( [id] => 4427305 [patent_doc_number] => 06226728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Dynamic allocation for efficient management of variable sized data within a nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 9/063954 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8596 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226728.pdf [firstpage_image] =>[orig_patent_app_number] => 063954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063954
Dynamic allocation for efficient management of variable sized data within a nonvolatile memory Apr 20, 1998 Issued
Array ( [id] => 4270200 [patent_doc_number] => 06223258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for implementing non-temporal loads' [patent_app_type] => 1 [patent_app_number] => 9/053528 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7476 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223258.pdf [firstpage_image] =>[orig_patent_app_number] => 053528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053528
Method and apparatus for implementing non-temporal loads Mar 30, 1998 Issued
Array ( [id] => 4269226 [patent_doc_number] => 06138219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access' [patent_app_type] => 1 [patent_app_number] => 9/049567 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6366 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138219.pdf [firstpage_image] =>[orig_patent_app_number] => 049567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049567
Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access Mar 26, 1998 Issued
Array ( [id] => 4422260 [patent_doc_number] => 06233663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Memory exclusive control device and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/049108 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6022 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233663.pdf [firstpage_image] =>[orig_patent_app_number] => 049108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049108
Memory exclusive control device and method therefor Mar 26, 1998 Issued
Array ( [id] => 4376379 [patent_doc_number] => 06219750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Disk drive having control mechanism to reduce or eliminate redundant write operations and the method thereof' [patent_app_type] => 1 [patent_app_number] => 9/049682 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5797 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219750.pdf [firstpage_image] =>[orig_patent_app_number] => 049682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049682
Disk drive having control mechanism to reduce or eliminate redundant write operations and the method thereof Mar 26, 1998 Issued
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