Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4292287 [patent_doc_number] => 06247102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Computer system employing memory controller and bridge interface permitting concurrent operation' [patent_app_type] => 1 [patent_app_number] => 9/047876 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 18362 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247102.pdf [firstpage_image] =>[orig_patent_app_number] => 047876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/047876
Computer system employing memory controller and bridge interface permitting concurrent operation Mar 24, 1998 Issued
Array ( [id] => 4422223 [patent_doc_number] => 06233659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Multi-port memory device with multiple modes of operation and improved expansion characteristics' [patent_app_type] => 1 [patent_app_number] => 9/035549 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4066 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233659.pdf [firstpage_image] =>[orig_patent_app_number] => 035549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035549
Multi-port memory device with multiple modes of operation and improved expansion characteristics Mar 4, 1998 Issued
Array ( [id] => 4333264 [patent_doc_number] => 06332183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method for recovery of useful areas of partially defective synchronous memory components' [patent_app_type] => 1 [patent_app_number] => 9/035739 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 2476 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332183.pdf [firstpage_image] =>[orig_patent_app_number] => 035739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035739
Method for recovery of useful areas of partially defective synchronous memory components Mar 4, 1998 Issued
Array ( [id] => 4273503 [patent_doc_number] => 06209061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Integrated hierarchical memory overlay having invariant address space span that inactivates a same address space span in main memory' [patent_app_type] => 1 [patent_app_number] => 9/032969 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2318 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209061.pdf [firstpage_image] =>[orig_patent_app_number] => 032969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032969
Integrated hierarchical memory overlay having invariant address space span that inactivates a same address space span in main memory Mar 1, 1998 Issued
Array ( [id] => 4424765 [patent_doc_number] => 06230246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Non-intrusive crash consistent copying in distributed storage systems without client cooperation' [patent_app_type] => 1 [patent_app_number] => 9/016320 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1756 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230246.pdf [firstpage_image] =>[orig_patent_app_number] => 016320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/016320
Non-intrusive crash consistent copying in distributed storage systems without client cooperation Jan 29, 1998 Issued
Array ( [id] => 4257646 [patent_doc_number] => 06145060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Data storage device with only internal addressing' [patent_app_type] => 1 [patent_app_number] => 9/000309 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6105 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145060.pdf [firstpage_image] =>[orig_patent_app_number] => 000309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000309
Data storage device with only internal addressing Jan 28, 1998 Issued
Array ( [id] => 4032693 [patent_doc_number] => 05907864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Data processing device with time-multiplexed memory bus' [patent_app_type] => 1 [patent_app_number] => 9/015260 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 20567 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907864.pdf [firstpage_image] =>[orig_patent_app_number] => 015260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015260
Data processing device with time-multiplexed memory bus Jan 28, 1998 Issued
Array ( [id] => 4239113 [patent_doc_number] => 06088778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method for manipulating disk partitions' [patent_app_type] => 1 [patent_app_number] => 9/002970 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 14567 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088778.pdf [firstpage_image] =>[orig_patent_app_number] => 002970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002970
Method for manipulating disk partitions Jan 4, 1998 Issued
Array ( [id] => 4260163 [patent_doc_number] => 06167485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'On-line data verification and repair in redundant storage systems' [patent_app_type] => 1 [patent_app_number] => 9/001857 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 12095 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167485.pdf [firstpage_image] =>[orig_patent_app_number] => 001857 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001857
On-line data verification and repair in redundant storage systems Dec 30, 1997 Issued
Array ( [id] => 4371159 [patent_doc_number] => 06216208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Prefetch queue responsive to read request sequences' [patent_app_type] => 1 [patent_app_number] => 8/999241 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3709 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216208.pdf [firstpage_image] =>[orig_patent_app_number] => 999241 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999241
Prefetch queue responsive to read request sequences Dec 28, 1997 Issued
Array ( [id] => 4273601 [patent_doc_number] => 06209068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Read line buffer and signaling protocol for processor' [patent_app_type] => 1 [patent_app_number] => 8/999242 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3288 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209068.pdf [firstpage_image] =>[orig_patent_app_number] => 999242 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999242
Read line buffer and signaling protocol for processor Dec 28, 1997 Issued
Array ( [id] => 4177303 [patent_doc_number] => 06105116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method and apparatus of controlling a disk cache during a degenerated mode of operation' [patent_app_type] => 1 [patent_app_number] => 8/996813 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9520 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105116.pdf [firstpage_image] =>[orig_patent_app_number] => 996813 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996813
Method and apparatus of controlling a disk cache during a degenerated mode of operation Dec 22, 1997 Issued
Array ( [id] => 4422160 [patent_doc_number] => 06233656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Bandwidth optimization cache' [patent_app_type] => 1 [patent_app_number] => 8/995950 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2362 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233656.pdf [firstpage_image] =>[orig_patent_app_number] => 995950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995950
Bandwidth optimization cache Dec 21, 1997 Issued
Array ( [id] => 4060961 [patent_doc_number] => 05895490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Computer system cache performance on write allocation cycles by immediately setting the modified bit true' [patent_app_type] => 1 [patent_app_number] => 8/989341 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 144 [patent_no_of_words] => 26791 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895490.pdf [firstpage_image] =>[orig_patent_app_number] => 989341 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989341
Computer system cache performance on write allocation cycles by immediately setting the modified bit true Dec 11, 1997 Issued
Array ( [id] => 4240115 [patent_doc_number] => 06012127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Multiprocessor computing apparatus with optional coherency directory' [patent_app_type] => 1 [patent_app_number] => 8/989371 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3068 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012127.pdf [firstpage_image] =>[orig_patent_app_number] => 989371 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989371
Multiprocessor computing apparatus with optional coherency directory Dec 11, 1997 Issued
Array ( [id] => 7029718 [patent_doc_number] => 20010014930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'MEMORY STRUCTURE' [patent_app_type] => new [patent_app_number] => 08/973425 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6666 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014930.pdf [firstpage_image] =>[orig_patent_app_number] => 08973425 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/973425
Memory structure for storage of memory vectors Dec 7, 1997 Issued
Array ( [id] => 4204024 [patent_doc_number] => 06151662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Data transaction typing for improved caching and prefetching characteristics' [patent_app_type] => 1 [patent_app_number] => 8/982720 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7513 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151662.pdf [firstpage_image] =>[orig_patent_app_number] => 982720 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982720
Data transaction typing for improved caching and prefetching characteristics Dec 1, 1997 Issued
Array ( [id] => 4138774 [patent_doc_number] => 06073213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method and apparatus for caching trace segments with multiple entry points' [patent_app_type] => 1 [patent_app_number] => 8/982097 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8566 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073213.pdf [firstpage_image] =>[orig_patent_app_number] => 982097 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982097
Method and apparatus for caching trace segments with multiple entry points Nov 30, 1997 Issued
Array ( [id] => 4252474 [patent_doc_number] => 06076144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method and apparatus for identifying potential entry points into trace segments' [patent_app_type] => 1 [patent_app_number] => 8/982083 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9362 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076144.pdf [firstpage_image] =>[orig_patent_app_number] => 982083 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982083
Method and apparatus for identifying potential entry points into trace segments Nov 30, 1997 Issued
Array ( [id] => 4057490 [patent_doc_number] => 05996055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method for reclaiming physical pages of memory while maintaining an even distribution of cache page addresses within an address space' [patent_app_type] => 1 [patent_app_number] => 8/979738 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14148 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996055.pdf [firstpage_image] =>[orig_patent_app_number] => 979738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979738
Method for reclaiming physical pages of memory while maintaining an even distribution of cache page addresses within an address space Nov 25, 1997 Issued
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