Sarira Camilla Pourbohloul

Array ( [id] => 4138818 [patent_doc_number] => 06073216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'System and method for reliable system shutdown after coherency corruption' [patent_app_type] => 1 [patent_app_number] => 8/980882 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073216.pdf [firstpage_image] =>[orig_patent_app_number] => 980882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152418 [patent_doc_number] => 06148366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Storage system which transfers a command and data corresponding to said command subsequent to said command' [patent_app_type] => 1 [patent_app_number] => 8/977342 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4081 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148366.pdf [firstpage_image] =>[orig_patent_app_number] => 977342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4403904 [patent_doc_number] => 06263404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system' [patent_app_type] => 1 [patent_app_number] => 8/976533 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12230 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263404.pdf [firstpage_image] =>[orig_patent_app_number] => 976533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4206781 [patent_doc_number] => 06131151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Processing high-speed digital datastreams with reduced memory' [patent_app_type] => 1 [patent_app_number] => 8/967880 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4584 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131151.pdf [firstpage_image] =>[orig_patent_app_number] => 967880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4011447 [patent_doc_number] => 05893148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'System and method for allocating cache memory storage space' [patent_app_type] => 1 [patent_app_number] => 8/966956 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5277 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893148.pdf [firstpage_image] =>[orig_patent_app_number] => 966956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4100975 [patent_doc_number] => 06018793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Single chip controller-memory device including feature-selectable bank I/O and architecture and methods suitable for implementing the same' [patent_app_type] => 1 [patent_app_number] => 8/957242 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5301 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018793.pdf [firstpage_image] =>[orig_patent_app_number] => 957242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4273558 [patent_doc_number] => 06209065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Mechanism for optimizing generation of commit-signals in a distributed shared-memory system' [patent_app_type] => 1 [patent_app_number] => 8/957230 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11481 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209065.pdf [firstpage_image] =>[orig_patent_app_number] => 957230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4215606 [patent_doc_number] => 06014732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Cache memory with reduced access time' [patent_app_type] => 1 [patent_app_number] => 8/955821 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3041 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014732.pdf [firstpage_image] =>[orig_patent_app_number] => 955821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4304766 [patent_doc_number] => 06269429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Microcomputer which writer data to memory based on an interrupt control mode' [patent_app_type] => 1 [patent_app_number] => 8/954611 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6884 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269429.pdf [firstpage_image] =>[orig_patent_app_number] => 954611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239061 [patent_doc_number] => 06088775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Data access controller and data access control method' [patent_app_type] => 1 [patent_app_number] => 8/954300 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4436 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088775.pdf [firstpage_image] =>[orig_patent_app_number] => 954300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4280664 [patent_doc_number] => 06260105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Memory controller with a plurality of memory address buses' [patent_app_type] => 1 [patent_app_number] => 8/954620 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2564 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260105.pdf [firstpage_image] =>[orig_patent_app_number] => 954620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4118245 [patent_doc_number] => 06098152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method and apparatus for miss sequence cache block replacement utilizing a most recently used state' [patent_app_type] => 1 [patent_app_number] => 8/953396 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 4958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098152.pdf [firstpage_image] =>[orig_patent_app_number] => 953396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971254 [patent_doc_number] => 06000022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method and apparatus for coupling signals between two circuits operating in different clock domains' [patent_app_type] => 1 [patent_app_number] => 8/948712 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5575 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000022.pdf [firstpage_image] =>[orig_patent_app_number] => 948712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237223 [patent_doc_number] => 06112276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Modular disk memory apparatus with high transfer rate' [patent_app_type] => 1 [patent_app_number] => 8/949102 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112276.pdf [firstpage_image] =>[orig_patent_app_number] => 949102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429010 [patent_doc_number] => 06513103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Method and apparatus for adjusting the performance of a synchronous memory system' [patent_app_type] => B1 [patent_app_number] => 08/948774 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4070 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513103.pdf [firstpage_image] =>[orig_patent_app_number] => 08948774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4033550 [patent_doc_number] => 05963971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method and apparatus for handling audit requests of logical volumes in a virtual media server' [patent_app_type] => 1 [patent_app_number] => 8/948366 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5251 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963971.pdf [firstpage_image] =>[orig_patent_app_number] => 948366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4427309 [patent_doc_number] => 06226732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Memory system architecture' [patent_app_type] => 1 [patent_app_number] => 8/942854 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226732.pdf [firstpage_image] =>[orig_patent_app_number] => 942854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4019783 [patent_doc_number] => 05860114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method and apparatus for managing snoop requests using snoop advisory cells' [patent_app_type] => 1 [patent_app_number] => 8/942255 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11050 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860114.pdf [firstpage_image] =>[orig_patent_app_number] => 942255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147443 [patent_doc_number] => 06128700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'System utilizing a DRAM array as a next level cache memory and method for operating same' [patent_app_type] => 1 [patent_app_number] => 8/942254 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12782 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128700.pdf [firstpage_image] =>[orig_patent_app_number] => 942254 [rel_patent_id] =>[rel_patent_doc_number] =>)