Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4223883 [patent_doc_number] => 06078994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'System for maintaining a shared cache in a multi-threaded computer environment' [patent_app_type] => 1 [patent_app_number] => 8/866518 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5566 [patent_no_of_claims] => 105 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078994.pdf [firstpage_image] =>[orig_patent_app_number] => 866518 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866518
System for maintaining a shared cache in a multi-threaded computer environment May 29, 1997 Issued
Array ( [id] => 4052230 [patent_doc_number] => 05943688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Automated database back-up within a data storage system using removable media' [patent_app_type] => 1 [patent_app_number] => 8/865523 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6224 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943688.pdf [firstpage_image] =>[orig_patent_app_number] => 865523 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865523
Automated database back-up within a data storage system using removable media May 28, 1997 Issued
Array ( [id] => 3815597 [patent_doc_number] => 05829018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Apparatus and method for writing data from a cache to a storage device' [patent_app_type] => 1 [patent_app_number] => 8/863101 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829018.pdf [firstpage_image] =>[orig_patent_app_number] => 863101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863101
Apparatus and method for writing data from a cache to a storage device May 22, 1997 Issued
Array ( [id] => 3833465 [patent_doc_number] => 05813036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Predictive snooping of cache memory for master-initiated accesses' [patent_app_type] => 1 [patent_app_number] => 8/851666 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 18449 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813036.pdf [firstpage_image] =>[orig_patent_app_number] => 851666 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851666
Predictive snooping of cache memory for master-initiated accesses May 5, 1997 Issued
Array ( [id] => 3805625 [patent_doc_number] => 05822756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Microprocessor cache memory way prediction based on the way of a previous memory read' [patent_app_type] => 1 [patent_app_number] => 8/839158 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 144 [patent_no_of_words] => 27009 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822756.pdf [firstpage_image] =>[orig_patent_app_number] => 839158 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839158
Microprocessor cache memory way prediction based on the way of a previous memory read Apr 22, 1997 Issued
Array ( [id] => 3969431 [patent_doc_number] => 05956747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Processor having a plurality of pipelines and a mechanism for maintaining coherency among register values in the pipelines' [patent_app_type] => 1 [patent_app_number] => 8/842861 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5620 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956747.pdf [firstpage_image] =>[orig_patent_app_number] => 842861 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842861
Processor having a plurality of pipelines and a mechanism for maintaining coherency among register values in the pipelines Apr 16, 1997 Issued
Array ( [id] => 3858533 [patent_doc_number] => 05745727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Linked caches memory for storing units of information' [patent_app_type] => 1 [patent_app_number] => 8/843315 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5469 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745727.pdf [firstpage_image] =>[orig_patent_app_number] => 843315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/843315
Linked caches memory for storing units of information Apr 14, 1997 Issued
Array ( [id] => 3960452 [patent_doc_number] => 05930831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Partition manipulation architecture supporting multiple file systems' [patent_app_type] => 1 [patent_app_number] => 8/834004 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8379 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930831.pdf [firstpage_image] =>[orig_patent_app_number] => 834004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834004
Partition manipulation architecture supporting multiple file systems Apr 10, 1997 Issued
Array ( [id] => 3805828 [patent_doc_number] => 05822767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method and apparartus for sharing a signal line between agents' [patent_app_type] => 1 [patent_app_number] => 8/824927 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13058 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822767.pdf [firstpage_image] =>[orig_patent_app_number] => 824927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824927
Method and apparartus for sharing a signal line between agents Mar 26, 1997 Issued
Array ( [id] => 3782145 [patent_doc_number] => 05845327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Cache coherency where multiple processors may access the same data over independent access paths' [patent_app_type] => 1 [patent_app_number] => 8/823839 [patent_app_country] => US [patent_app_date] => 1997-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 9478 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845327.pdf [firstpage_image] =>[orig_patent_app_number] => 823839 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/823839
Cache coherency where multiple processors may access the same data over independent access paths Mar 24, 1997 Issued
Array ( [id] => 3759025 [patent_doc_number] => 05787487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Information storage system for converting data at transfer' [patent_app_type] => 1 [patent_app_number] => 8/822146 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 16019 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787487.pdf [firstpage_image] =>[orig_patent_app_number] => 822146 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822146
Information storage system for converting data at transfer Mar 20, 1997 Issued
Array ( [id] => 4001820 [patent_doc_number] => 05950227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'CPU write-back cache coherency mechanism that transfers data from a cache memory to a main memory after access of the main memory by an alternative bus master' [patent_app_type] => 1 [patent_app_number] => 8/826433 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5286 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950227.pdf [firstpage_image] =>[orig_patent_app_number] => 826433 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826433
CPU write-back cache coherency mechanism that transfers data from a cache memory to a main memory after access of the main memory by an alternative bus master Mar 19, 1997 Issued
Array ( [id] => 3798588 [patent_doc_number] => 05809558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Method and data storage system for storing data in blocks without file reallocation before erasure' [patent_app_type] => 1 [patent_app_number] => 8/819688 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5795 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809558.pdf [firstpage_image] =>[orig_patent_app_number] => 819688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/819688
Method and data storage system for storing data in blocks without file reallocation before erasure Mar 16, 1997 Issued
Array ( [id] => 3815706 [patent_doc_number] => 05829026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Method and structure for implementing a cache memory using a DRAM array' [patent_app_type] => 1 [patent_app_number] => 8/812000 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8890 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829026.pdf [firstpage_image] =>[orig_patent_app_number] => 812000 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812000
Method and structure for implementing a cache memory using a DRAM array Mar 4, 1997 Issued
Array ( [id] => 3913415 [patent_doc_number] => 05835952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Monolithic image data memory system and access method that utilizes multiple banks to hide precharge time' [patent_app_type] => 1 [patent_app_number] => 8/808938 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11613 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835952.pdf [firstpage_image] =>[orig_patent_app_number] => 808938 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/808938
Monolithic image data memory system and access method that utilizes multiple banks to hide precharge time Feb 27, 1997 Issued
Array ( [id] => 4373811 [patent_doc_number] => 06202136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method of creating an internally consistent copy of an actively updated data set without specialized caching hardware' [patent_app_type] => 1 [patent_app_number] => 8/807313 [patent_app_country] => US [patent_app_date] => 1997-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 6659 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202136.pdf [firstpage_image] =>[orig_patent_app_number] => 807313 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/807313
Method of creating an internally consistent copy of an actively updated data set without specialized caching hardware Feb 26, 1997 Issued
Array ( [id] => 3995957 [patent_doc_number] => 05918241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method and apparatus for setting a plurality of addresses' [patent_app_type] => 1 [patent_app_number] => 8/804326 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4407 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918241.pdf [firstpage_image] =>[orig_patent_app_number] => 804326 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804326
Method and apparatus for setting a plurality of addresses Feb 20, 1997 Issued
Array ( [id] => 3833494 [patent_doc_number] => 05813038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Memory controller having precharge prediction based on processor and PC bus cycles' [patent_app_type] => 1 [patent_app_number] => 8/802295 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 14692 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813038.pdf [firstpage_image] =>[orig_patent_app_number] => 802295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802295
Memory controller having precharge prediction based on processor and PC bus cycles Feb 17, 1997 Issued
Array ( [id] => 3798465 [patent_doc_number] => 05809549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Burst SRAMs for use with a high speed clock' [patent_app_type] => 1 [patent_app_number] => 8/801738 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809549.pdf [firstpage_image] =>[orig_patent_app_number] => 801738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801738
Burst SRAMs for use with a high speed clock Feb 13, 1997 Issued
Array ( [id] => 3954691 [patent_doc_number] => 05873124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Virtual memory scratch pages' [patent_app_type] => 1 [patent_app_number] => 8/796409 [patent_app_country] => US [patent_app_date] => 1997-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3489 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/873/05873124.pdf [firstpage_image] =>[orig_patent_app_number] => 796409 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/796409
Virtual memory scratch pages Feb 5, 1997 Issued
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