Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3944292 [patent_doc_number] => 05946708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Automated cache manager for storage devices' [patent_app_type] => 1 [patent_app_number] => 8/788312 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7348 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946708.pdf [firstpage_image] =>[orig_patent_app_number] => 788312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/788312
Automated cache manager for storage devices Jan 23, 1997 Issued
Array ( [id] => 3888783 [patent_doc_number] => 05893928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Data movement apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/786463 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2004 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893928.pdf [firstpage_image] =>[orig_patent_app_number] => 786463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786463
Data movement apparatus and method Jan 20, 1997 Issued
08/780963 METHOD AND APPARATUS FOR MANAGING SNOOP REQUESTS USING SNOOP ADVISORY CELLS Jan 8, 1997 Abandoned
Array ( [id] => 4239138 [patent_doc_number] => 06088779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'System and method for execution management of computer programs' [patent_app_type] => 1 [patent_app_number] => 8/778213 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3952 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088779.pdf [firstpage_image] =>[orig_patent_app_number] => 778213 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778213
System and method for execution management of computer programs Dec 29, 1996 Issued
Array ( [id] => 4044848 [patent_doc_number] => 05903913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Method and apparatus for storage system management in a multi-host environment' [patent_app_type] => 1 [patent_app_number] => 8/770348 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3227 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903913.pdf [firstpage_image] =>[orig_patent_app_number] => 770348 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770348
Method and apparatus for storage system management in a multi-host environment Dec 19, 1996 Issued
Array ( [id] => 4032733 [patent_doc_number] => 05907866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Block address translation circuit using two-bit to four-bit encoder' [patent_app_type] => 1 [patent_app_number] => 8/770220 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3280 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907866.pdf [firstpage_image] =>[orig_patent_app_number] => 770220 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770220
Block address translation circuit using two-bit to four-bit encoder Dec 18, 1996 Issued
Array ( [id] => 3918563 [patent_doc_number] => 05751996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method and apparatus for processing memory-type information within a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/767799 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15981 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751996.pdf [firstpage_image] =>[orig_patent_app_number] => 767799 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/767799
Method and apparatus for processing memory-type information within a microprocessor Dec 16, 1996 Issued
Array ( [id] => 3913539 [patent_doc_number] => 05835960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus' [patent_app_type] => 1 [patent_app_number] => 8/762225 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4906 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835960.pdf [firstpage_image] =>[orig_patent_app_number] => 762225 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/762225
Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus Dec 8, 1996 Issued
Array ( [id] => 3971087 [patent_doc_number] => 06000011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Multi-entry fully associative transition cache' [patent_app_type] => 1 [patent_app_number] => 8/761378 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14084 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000011.pdf [firstpage_image] =>[orig_patent_app_number] => 761378 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761378
Multi-entry fully associative transition cache Dec 8, 1996 Issued
Array ( [id] => 3971116 [patent_doc_number] => 06000012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method and apparatus for prioritizing and routing commands from a command source to a command sink' [patent_app_type] => 1 [patent_app_number] => 8/761380 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14063 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000012.pdf [firstpage_image] =>[orig_patent_app_number] => 761380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761380
Method and apparatus for prioritizing and routing commands from a command source to a command sink Dec 8, 1996 Issued
Array ( [id] => 4011558 [patent_doc_number] => 05893155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Cache memory for efficient data logging' [patent_app_type] => 1 [patent_app_number] => 8/757700 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 24181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893155.pdf [firstpage_image] =>[orig_patent_app_number] => 757700 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757700
Cache memory for efficient data logging Dec 2, 1996 Issued
Array ( [id] => 3900878 [patent_doc_number] => 05749089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Cache-memory system having multidimensional spread cache' [patent_app_type] => 1 [patent_app_number] => 8/757081 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 6705 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749089.pdf [firstpage_image] =>[orig_patent_app_number] => 757081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757081
Cache-memory system having multidimensional spread cache Nov 25, 1996 Issued
Array ( [id] => 4019856 [patent_doc_number] => 05860118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'SRAM write partitioning' [patent_app_type] => 1 [patent_app_number] => 8/756270 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3512 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860118.pdf [firstpage_image] =>[orig_patent_app_number] => 756270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756270
SRAM write partitioning Nov 24, 1996 Issued
Array ( [id] => 4092399 [patent_doc_number] => 05966735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Array index chaining for tree structure save and restore in a process swapping system' [patent_app_type] => 1 [patent_app_number] => 8/754868 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 15221 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966735.pdf [firstpage_image] =>[orig_patent_app_number] => 754868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/754868
Array index chaining for tree structure save and restore in a process swapping system Nov 21, 1996 Issued
Array ( [id] => 4011544 [patent_doc_number] => 05893154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'CPU write-back cache coherency mechanism that transeers data from a cache memory to a main memory before access of the main memory by an alternate bus master' [patent_app_type] => 1 [patent_app_number] => 8/752008 [patent_app_country] => US [patent_app_date] => 1996-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5221 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893154.pdf [firstpage_image] =>[orig_patent_app_number] => 752008 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752008
CPU write-back cache coherency mechanism that transeers data from a cache memory to a main memory before access of the main memory by an alternate bus master Nov 14, 1996 Issued
Array ( [id] => 4060918 [patent_doc_number] => 05895487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Integrated processing and L2 DRAM cache' [patent_app_type] => 1 [patent_app_number] => 8/748300 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10145 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895487.pdf [firstpage_image] =>[orig_patent_app_number] => 748300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748300
Integrated processing and L2 DRAM cache Nov 12, 1996 Issued
Array ( [id] => 3961638 [patent_doc_number] => 05974514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Controlling SDRAM memory by using truncated burst read-modify-write memory operations' [patent_app_type] => 1 [patent_app_number] => 8/747320 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4465 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974514.pdf [firstpage_image] =>[orig_patent_app_number] => 747320 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747320
Controlling SDRAM memory by using truncated burst read-modify-write memory operations Nov 11, 1996 Issued
Array ( [id] => 3900947 [patent_doc_number] => 05749094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Invalid write recovery apparatus and method within cache memory' [patent_app_type] => 1 [patent_app_number] => 8/747196 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3835 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749094.pdf [firstpage_image] =>[orig_patent_app_number] => 747196 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747196
Invalid write recovery apparatus and method within cache memory Nov 11, 1996 Issued
Array ( [id] => 3758652 [patent_doc_number] => 05787460 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Disk array apparatus that only calculates new parity after a predetermined number of write requests' [patent_app_type] => 1 [patent_app_number] => 8/746154 [patent_app_country] => US [patent_app_date] => 1996-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 49 [patent_no_of_words] => 16012 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787460.pdf [firstpage_image] =>[orig_patent_app_number] => 746154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746154
Disk array apparatus that only calculates new parity after a predetermined number of write requests Nov 5, 1996 Issued
Array ( [id] => 4026836 [patent_doc_number] => 05890198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Intelligent refresh controller for dynamic memory devices' [patent_app_type] => 1 [patent_app_number] => 8/735324 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3590 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890198.pdf [firstpage_image] =>[orig_patent_app_number] => 735324 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735324
Intelligent refresh controller for dynamic memory devices Oct 21, 1996 Issued
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